/*
 * Freescale PINCTRL Register Definitions
 *
 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 * This file is created by xml file. Don't Edit it.
 *
 * Xml Revision: 1.19
 * Template revision: 26195
 */

#ifndef __ARCH_ARM___PINCTRL_H
#define __ARCH_ARM___PINCTRL_H


#define HW_PINCTRL_CTRL	(0x00000000)
#define HW_PINCTRL_CTRL_SET	(0x00000004)
#define HW_PINCTRL_CTRL_CLR	(0x00000008)
#define HW_PINCTRL_CTRL_TOG	(0x0000000c)

#define BM_PINCTRL_CTRL_SFTRST	0x80000000
#define BM_PINCTRL_CTRL_CLKGATE	0x40000000
#define BP_PINCTRL_CTRL_RSRVD2	25
#define BM_PINCTRL_CTRL_RSRVD2	0x3E000000
#define BF_PINCTRL_CTRL_RSRVD2(v)  \
		(((v) << 25) & BM_PINCTRL_CTRL_RSRVD2)
#define BM_PINCTRL_CTRL_PRESENT4	0x01000000
#define BM_PINCTRL_CTRL_PRESENT3	0x00800000
#define BM_PINCTRL_CTRL_PRESENT2	0x00400000
#define BM_PINCTRL_CTRL_PRESENT1	0x00200000
#define BM_PINCTRL_CTRL_PRESENT0	0x00100000
#define BP_PINCTRL_CTRL_RSRVD1	5
#define BM_PINCTRL_CTRL_RSRVD1	0x000FFFE0
#define BF_PINCTRL_CTRL_RSRVD1(v)  \
		(((v) << 5) & BM_PINCTRL_CTRL_RSRVD1)
#define BM_PINCTRL_CTRL_IRQOUT4	0x00000010
#define BM_PINCTRL_CTRL_IRQOUT3	0x00000008
#define BM_PINCTRL_CTRL_IRQOUT2	0x00000004
#define BM_PINCTRL_CTRL_IRQOUT1	0x00000002
#define BM_PINCTRL_CTRL_IRQOUT0	0x00000001

#define HW_PINCTRL_MUXSEL0	(0x00000100)
#define HW_PINCTRL_MUXSEL0_SET	(0x00000104)
#define HW_PINCTRL_MUXSEL0_CLR	(0x00000108)
#define HW_PINCTRL_MUXSEL0_TOG	(0x0000010c)

#define BP_PINCTRL_MUXSEL0_RSRVD0	16
#define BM_PINCTRL_MUXSEL0_RSRVD0	0xFFFF0000
#define BF_PINCTRL_MUXSEL0_RSRVD0(v) \
		(((v) << 16) & BM_PINCTRL_MUXSEL0_RSRVD0)
#define BP_PINCTRL_MUXSEL0_BANK0_PIN07	14
#define BM_PINCTRL_MUXSEL0_BANK0_PIN07	0x0000C000
#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07)
#define BP_PINCTRL_MUXSEL0_BANK0_PIN06	12
#define BM_PINCTRL_MUXSEL0_BANK0_PIN06	0x00003000
#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06)
#define BP_PINCTRL_MUXSEL0_BANK0_PIN05	10
#define BM_PINCTRL_MUXSEL0_BANK0_PIN05	0x00000C00
#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05)
#define BP_PINCTRL_MUXSEL0_BANK0_PIN04	8
#define BM_PINCTRL_MUXSEL0_BANK0_PIN04	0x00000300
#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04)
#define BP_PINCTRL_MUXSEL0_BANK0_PIN03	6
#define BM_PINCTRL_MUXSEL0_BANK0_PIN03	0x000000C0
#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03)
#define BP_PINCTRL_MUXSEL0_BANK0_PIN02	4
#define BM_PINCTRL_MUXSEL0_BANK0_PIN02	0x00000030
#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02)
#define BP_PINCTRL_MUXSEL0_BANK0_PIN01	2
#define BM_PINCTRL_MUXSEL0_BANK0_PIN01	0x0000000C
#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01)
#define BP_PINCTRL_MUXSEL0_BANK0_PIN00	0
#define BM_PINCTRL_MUXSEL0_BANK0_PIN00	0x00000003
#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00)

#define HW_PINCTRL_MUXSEL1	(0x00000110)
#define HW_PINCTRL_MUXSEL1_SET	(0x00000114)
#define HW_PINCTRL_MUXSEL1_CLR	(0x00000118)
#define HW_PINCTRL_MUXSEL1_TOG	(0x0000011c)

#define BP_PINCTRL_MUXSEL1_RSRVD0	26
#define BM_PINCTRL_MUXSEL1_RSRVD0	0xFC000000
#define BF_PINCTRL_MUXSEL1_RSRVD0(v) \
		(((v) << 26) & BM_PINCTRL_MUXSEL1_RSRVD0)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN28	24
#define BM_PINCTRL_MUXSEL1_BANK0_PIN28	0x03000000
#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN27	22
#define BM_PINCTRL_MUXSEL1_BANK0_PIN27	0x00C00000
#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN26	20
#define BM_PINCTRL_MUXSEL1_BANK0_PIN26	0x00300000
#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN25	18
#define BM_PINCTRL_MUXSEL1_BANK0_PIN25	0x000C0000
#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN24	16
#define BM_PINCTRL_MUXSEL1_BANK0_PIN24	0x00030000
#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN23	14
#define BM_PINCTRL_MUXSEL1_BANK0_PIN23	0x0000C000
#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN22	12
#define BM_PINCTRL_MUXSEL1_BANK0_PIN22	0x00003000
#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN21	10
#define BM_PINCTRL_MUXSEL1_BANK0_PIN21	0x00000C00
#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN20	8
#define BM_PINCTRL_MUXSEL1_BANK0_PIN20	0x00000300
#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN19	6
#define BM_PINCTRL_MUXSEL1_BANK0_PIN19	0x000000C0
#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN18	4
#define BM_PINCTRL_MUXSEL1_BANK0_PIN18	0x00000030
#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN17	2
#define BM_PINCTRL_MUXSEL1_BANK0_PIN17	0x0000000C
#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17)
#define BP_PINCTRL_MUXSEL1_BANK0_PIN16	0
#define BM_PINCTRL_MUXSEL1_BANK0_PIN16	0x00000003
#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16)

#define HW_PINCTRL_MUXSEL2	(0x00000120)
#define HW_PINCTRL_MUXSEL2_SET	(0x00000124)
#define HW_PINCTRL_MUXSEL2_CLR	(0x00000128)
#define HW_PINCTRL_MUXSEL2_TOG	(0x0000012c)

#define BP_PINCTRL_MUXSEL2_BANK1_PIN15	30
#define BM_PINCTRL_MUXSEL2_BANK1_PIN15	0xC0000000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \
		(((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN14	28
#define BM_PINCTRL_MUXSEL2_BANK1_PIN14	0x30000000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v)  \
		(((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN13	26
#define BM_PINCTRL_MUXSEL2_BANK1_PIN13	0x0C000000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v)  \
		(((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN12	24
#define BM_PINCTRL_MUXSEL2_BANK1_PIN12	0x03000000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN11	22
#define BM_PINCTRL_MUXSEL2_BANK1_PIN11	0x00C00000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN10	20
#define BM_PINCTRL_MUXSEL2_BANK1_PIN10	0x00300000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN09	18
#define BM_PINCTRL_MUXSEL2_BANK1_PIN09	0x000C0000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN08	16
#define BM_PINCTRL_MUXSEL2_BANK1_PIN08	0x00030000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN07	14
#define BM_PINCTRL_MUXSEL2_BANK1_PIN07	0x0000C000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN06	12
#define BM_PINCTRL_MUXSEL2_BANK1_PIN06	0x00003000
#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN05	10
#define BM_PINCTRL_MUXSEL2_BANK1_PIN05	0x00000C00
#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN04	8
#define BM_PINCTRL_MUXSEL2_BANK1_PIN04	0x00000300
#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN03	6
#define BM_PINCTRL_MUXSEL2_BANK1_PIN03	0x000000C0
#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN02	4
#define BM_PINCTRL_MUXSEL2_BANK1_PIN02	0x00000030
#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN01	2
#define BM_PINCTRL_MUXSEL2_BANK1_PIN01	0x0000000C
#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01)
#define BP_PINCTRL_MUXSEL2_BANK1_PIN00	0
#define BM_PINCTRL_MUXSEL2_BANK1_PIN00	0x00000003
#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00)

#define HW_PINCTRL_MUXSEL3	(0x00000130)
#define HW_PINCTRL_MUXSEL3_SET	(0x00000134)
#define HW_PINCTRL_MUXSEL3_CLR	(0x00000138)
#define HW_PINCTRL_MUXSEL3_TOG	(0x0000013c)

#define BP_PINCTRL_MUXSEL3_BANK1_PIN31	30
#define BM_PINCTRL_MUXSEL3_BANK1_PIN31	0xC0000000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN31(v) \
		(((v) << 30) & BM_PINCTRL_MUXSEL3_BANK1_PIN31)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN30	28
#define BM_PINCTRL_MUXSEL3_BANK1_PIN30	0x30000000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v)  \
		(((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN29	26
#define BM_PINCTRL_MUXSEL3_BANK1_PIN29	0x0C000000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v)  \
		(((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN28	24
#define BM_PINCTRL_MUXSEL3_BANK1_PIN28	0x03000000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN27	22
#define BM_PINCTRL_MUXSEL3_BANK1_PIN27	0x00C00000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN26	20
#define BM_PINCTRL_MUXSEL3_BANK1_PIN26	0x00300000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN25	18
#define BM_PINCTRL_MUXSEL3_BANK1_PIN25	0x000C0000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN24	16
#define BM_PINCTRL_MUXSEL3_BANK1_PIN24	0x00030000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN23	14
#define BM_PINCTRL_MUXSEL3_BANK1_PIN23	0x0000C000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN22	12
#define BM_PINCTRL_MUXSEL3_BANK1_PIN22	0x00003000
#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN21	10
#define BM_PINCTRL_MUXSEL3_BANK1_PIN21	0x00000C00
#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN20	8
#define BM_PINCTRL_MUXSEL3_BANK1_PIN20	0x00000300
#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN19	6
#define BM_PINCTRL_MUXSEL3_BANK1_PIN19	0x000000C0
#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN18	4
#define BM_PINCTRL_MUXSEL3_BANK1_PIN18	0x00000030
#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN17	2
#define BM_PINCTRL_MUXSEL3_BANK1_PIN17	0x0000000C
#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17)
#define BP_PINCTRL_MUXSEL3_BANK1_PIN16	0
#define BM_PINCTRL_MUXSEL3_BANK1_PIN16	0x00000003
#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16)

#define HW_PINCTRL_MUXSEL4	(0x00000140)
#define HW_PINCTRL_MUXSEL4_SET	(0x00000144)
#define HW_PINCTRL_MUXSEL4_CLR	(0x00000148)
#define HW_PINCTRL_MUXSEL4_TOG	(0x0000014c)

#define BP_PINCTRL_MUXSEL4_BANK2_PIN15	30
#define BM_PINCTRL_MUXSEL4_BANK2_PIN15	0xC0000000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \
		(((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN14	28
#define BM_PINCTRL_MUXSEL4_BANK2_PIN14	0x30000000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v)  \
		(((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN13	26
#define BM_PINCTRL_MUXSEL4_BANK2_PIN13	0x0C000000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v)  \
		(((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN12	24
#define BM_PINCTRL_MUXSEL4_BANK2_PIN12	0x03000000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12)
#define BP_PINCTRL_MUXSEL4_RSRVD0	22
#define BM_PINCTRL_MUXSEL4_RSRVD0	0x00C00000
#define BF_PINCTRL_MUXSEL4_RSRVD0(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL4_RSRVD0)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN10	20
#define BM_PINCTRL_MUXSEL4_BANK2_PIN10	0x00300000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN09	18
#define BM_PINCTRL_MUXSEL4_BANK2_PIN09	0x000C0000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN08	16
#define BM_PINCTRL_MUXSEL4_BANK2_PIN08	0x00030000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN07	14
#define BM_PINCTRL_MUXSEL4_BANK2_PIN07	0x0000C000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN06	12
#define BM_PINCTRL_MUXSEL4_BANK2_PIN06	0x00003000
#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN05	10
#define BM_PINCTRL_MUXSEL4_BANK2_PIN05	0x00000C00
#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN04	8
#define BM_PINCTRL_MUXSEL4_BANK2_PIN04	0x00000300
#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN03	6
#define BM_PINCTRL_MUXSEL4_BANK2_PIN03	0x000000C0
#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN02	4
#define BM_PINCTRL_MUXSEL4_BANK2_PIN02	0x00000030
#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN01	2
#define BM_PINCTRL_MUXSEL4_BANK2_PIN01	0x0000000C
#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01)
#define BP_PINCTRL_MUXSEL4_BANK2_PIN00	0
#define BM_PINCTRL_MUXSEL4_BANK2_PIN00	0x00000003
#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00)

#define HW_PINCTRL_MUXSEL5	(0x00000150)
#define HW_PINCTRL_MUXSEL5_SET	(0x00000154)
#define HW_PINCTRL_MUXSEL5_CLR	(0x00000158)
#define HW_PINCTRL_MUXSEL5_TOG	(0x0000015c)

#define BP_PINCTRL_MUXSEL5_RSRVD1	24
#define BM_PINCTRL_MUXSEL5_RSRVD1	0xFF000000
#define BF_PINCTRL_MUXSEL5_RSRVD1(v) \
		(((v) << 24) & BM_PINCTRL_MUXSEL5_RSRVD1)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN27	22
#define BM_PINCTRL_MUXSEL5_BANK2_PIN27	0x00C00000
#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN26	20
#define BM_PINCTRL_MUXSEL5_BANK2_PIN26	0x00300000
#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN25	18
#define BM_PINCTRL_MUXSEL5_BANK2_PIN25	0x000C0000
#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN24	16
#define BM_PINCTRL_MUXSEL5_BANK2_PIN24	0x00030000
#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24)
#define BP_PINCTRL_MUXSEL5_RSRVD0	12
#define BM_PINCTRL_MUXSEL5_RSRVD0	0x0000F000
#define BF_PINCTRL_MUXSEL5_RSRVD0(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL5_RSRVD0)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN21	10
#define BM_PINCTRL_MUXSEL5_BANK2_PIN21	0x00000C00
#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN20	8
#define BM_PINCTRL_MUXSEL5_BANK2_PIN20	0x00000300
#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN19	6
#define BM_PINCTRL_MUXSEL5_BANK2_PIN19	0x000000C0
#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN18	4
#define BM_PINCTRL_MUXSEL5_BANK2_PIN18	0x00000030
#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN17	2
#define BM_PINCTRL_MUXSEL5_BANK2_PIN17	0x0000000C
#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17)
#define BP_PINCTRL_MUXSEL5_BANK2_PIN16	0
#define BM_PINCTRL_MUXSEL5_BANK2_PIN16	0x00000003
#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16)

#define HW_PINCTRL_MUXSEL6	(0x00000160)
#define HW_PINCTRL_MUXSEL6_SET	(0x00000164)
#define HW_PINCTRL_MUXSEL6_CLR	(0x00000168)
#define HW_PINCTRL_MUXSEL6_TOG	(0x0000016c)

#define BP_PINCTRL_MUXSEL6_BANK3_PIN15	30
#define BM_PINCTRL_MUXSEL6_BANK3_PIN15	0xC0000000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \
		(((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN14	28
#define BM_PINCTRL_MUXSEL6_BANK3_PIN14	0x30000000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v)  \
		(((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN13	26
#define BM_PINCTRL_MUXSEL6_BANK3_PIN13	0x0C000000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v)  \
		(((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN12	24
#define BM_PINCTRL_MUXSEL6_BANK3_PIN12	0x03000000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN11	22
#define BM_PINCTRL_MUXSEL6_BANK3_PIN11	0x00C00000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN10	20
#define BM_PINCTRL_MUXSEL6_BANK3_PIN10	0x00300000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN09	18
#define BM_PINCTRL_MUXSEL6_BANK3_PIN09	0x000C0000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN08	16
#define BM_PINCTRL_MUXSEL6_BANK3_PIN08	0x00030000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN07	14
#define BM_PINCTRL_MUXSEL6_BANK3_PIN07	0x0000C000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN06	12
#define BM_PINCTRL_MUXSEL6_BANK3_PIN06	0x00003000
#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN05	10
#define BM_PINCTRL_MUXSEL6_BANK3_PIN05	0x00000C00
#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN04	8
#define BM_PINCTRL_MUXSEL6_BANK3_PIN04	0x00000300
#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN03	6
#define BM_PINCTRL_MUXSEL6_BANK3_PIN03	0x000000C0
#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN02	4
#define BM_PINCTRL_MUXSEL6_BANK3_PIN02	0x00000030
#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN01	2
#define BM_PINCTRL_MUXSEL6_BANK3_PIN01	0x0000000C
#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01)
#define BP_PINCTRL_MUXSEL6_BANK3_PIN00	0
#define BM_PINCTRL_MUXSEL6_BANK3_PIN00	0x00000003
#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00)

#define HW_PINCTRL_MUXSEL7	(0x00000170)
#define HW_PINCTRL_MUXSEL7_SET	(0x00000174)
#define HW_PINCTRL_MUXSEL7_CLR	(0x00000178)
#define HW_PINCTRL_MUXSEL7_TOG	(0x0000017c)

#define BP_PINCTRL_MUXSEL7_RSRVD1	30
#define BM_PINCTRL_MUXSEL7_RSRVD1	0xC0000000
#define BF_PINCTRL_MUXSEL7_RSRVD1(v) \
		(((v) << 30) & BM_PINCTRL_MUXSEL7_RSRVD1)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN30	28
#define BM_PINCTRL_MUXSEL7_BANK3_PIN30	0x30000000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN30(v)  \
		(((v) << 28) & BM_PINCTRL_MUXSEL7_BANK3_PIN30)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN29	26
#define BM_PINCTRL_MUXSEL7_BANK3_PIN29	0x0C000000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN29(v)  \
		(((v) << 26) & BM_PINCTRL_MUXSEL7_BANK3_PIN29)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN28	24
#define BM_PINCTRL_MUXSEL7_BANK3_PIN28	0x03000000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN28(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL7_BANK3_PIN28)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN27	22
#define BM_PINCTRL_MUXSEL7_BANK3_PIN27	0x00C00000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN27(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL7_BANK3_PIN27)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN26	20
#define BM_PINCTRL_MUXSEL7_BANK3_PIN26	0x00300000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN26(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL7_BANK3_PIN26)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN25	18
#define BM_PINCTRL_MUXSEL7_BANK3_PIN25	0x000C0000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN25(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL7_BANK3_PIN25)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN24	16
#define BM_PINCTRL_MUXSEL7_BANK3_PIN24	0x00030000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN24(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL7_BANK3_PIN24)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN23	14
#define BM_PINCTRL_MUXSEL7_BANK3_PIN23	0x0000C000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN23(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL7_BANK3_PIN23)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN22	12
#define BM_PINCTRL_MUXSEL7_BANK3_PIN22	0x00003000
#define BF_PINCTRL_MUXSEL7_BANK3_PIN22(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL7_BANK3_PIN22)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN21	10
#define BM_PINCTRL_MUXSEL7_BANK3_PIN21	0x00000C00
#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN20	8
#define BM_PINCTRL_MUXSEL7_BANK3_PIN20	0x00000300
#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20)
#define BP_PINCTRL_MUXSEL7_RSRVD0	6
#define BM_PINCTRL_MUXSEL7_RSRVD0	0x000000C0
#define BF_PINCTRL_MUXSEL7_RSRVD0(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL7_RSRVD0)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN18	4
#define BM_PINCTRL_MUXSEL7_BANK3_PIN18	0x00000030
#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN17	2
#define BM_PINCTRL_MUXSEL7_BANK3_PIN17	0x0000000C
#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17)
#define BP_PINCTRL_MUXSEL7_BANK3_PIN16	0
#define BM_PINCTRL_MUXSEL7_BANK3_PIN16	0x00000003
#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16)

#define HW_PINCTRL_MUXSEL8	(0x00000180)
#define HW_PINCTRL_MUXSEL8_SET	(0x00000184)
#define HW_PINCTRL_MUXSEL8_CLR	(0x00000188)
#define HW_PINCTRL_MUXSEL8_TOG	(0x0000018c)

#define BP_PINCTRL_MUXSEL8_BANK4_PIN15	30
#define BM_PINCTRL_MUXSEL8_BANK4_PIN15	0xC0000000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN15(v) \
		(((v) << 30) & BM_PINCTRL_MUXSEL8_BANK4_PIN15)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN14	28
#define BM_PINCTRL_MUXSEL8_BANK4_PIN14	0x30000000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN14(v)  \
		(((v) << 28) & BM_PINCTRL_MUXSEL8_BANK4_PIN14)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN13	26
#define BM_PINCTRL_MUXSEL8_BANK4_PIN13	0x0C000000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN13(v)  \
		(((v) << 26) & BM_PINCTRL_MUXSEL8_BANK4_PIN13)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN12	24
#define BM_PINCTRL_MUXSEL8_BANK4_PIN12	0x03000000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN12(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL8_BANK4_PIN12)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN11	22
#define BM_PINCTRL_MUXSEL8_BANK4_PIN11	0x00C00000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN11(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL8_BANK4_PIN11)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN10	20
#define BM_PINCTRL_MUXSEL8_BANK4_PIN10	0x00300000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN10(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL8_BANK4_PIN10)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN09	18
#define BM_PINCTRL_MUXSEL8_BANK4_PIN09	0x000C0000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN09(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL8_BANK4_PIN09)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN08	16
#define BM_PINCTRL_MUXSEL8_BANK4_PIN08	0x00030000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN08(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL8_BANK4_PIN08)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN07	14
#define BM_PINCTRL_MUXSEL8_BANK4_PIN07	0x0000C000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN07(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL8_BANK4_PIN07)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN06	12
#define BM_PINCTRL_MUXSEL8_BANK4_PIN06	0x00003000
#define BF_PINCTRL_MUXSEL8_BANK4_PIN06(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL8_BANK4_PIN06)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN05	10
#define BM_PINCTRL_MUXSEL8_BANK4_PIN05	0x00000C00
#define BF_PINCTRL_MUXSEL8_BANK4_PIN05(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL8_BANK4_PIN05)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN04	8
#define BM_PINCTRL_MUXSEL8_BANK4_PIN04	0x00000300
#define BF_PINCTRL_MUXSEL8_BANK4_PIN04(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL8_BANK4_PIN04)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN03	6
#define BM_PINCTRL_MUXSEL8_BANK4_PIN03	0x000000C0
#define BF_PINCTRL_MUXSEL8_BANK4_PIN03(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL8_BANK4_PIN03)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN02	4
#define BM_PINCTRL_MUXSEL8_BANK4_PIN02	0x00000030
#define BF_PINCTRL_MUXSEL8_BANK4_PIN02(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL8_BANK4_PIN02)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN01	2
#define BM_PINCTRL_MUXSEL8_BANK4_PIN01	0x0000000C
#define BF_PINCTRL_MUXSEL8_BANK4_PIN01(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL8_BANK4_PIN01)
#define BP_PINCTRL_MUXSEL8_BANK4_PIN00	0
#define BM_PINCTRL_MUXSEL8_BANK4_PIN00	0x00000003
#define BF_PINCTRL_MUXSEL8_BANK4_PIN00(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL8_BANK4_PIN00)

#define HW_PINCTRL_MUXSEL9	(0x00000190)
#define HW_PINCTRL_MUXSEL9_SET	(0x00000194)
#define HW_PINCTRL_MUXSEL9_CLR	(0x00000198)
#define HW_PINCTRL_MUXSEL9_TOG	(0x0000019c)

#define BP_PINCTRL_MUXSEL9_RSRVD1	10
#define BM_PINCTRL_MUXSEL9_RSRVD1	0xFFFFFC00
#define BF_PINCTRL_MUXSEL9_RSRVD1(v) \
		(((v) << 10) & BM_PINCTRL_MUXSEL9_RSRVD1)
#define BP_PINCTRL_MUXSEL9_BANK4_PIN20	8
#define BM_PINCTRL_MUXSEL9_BANK4_PIN20	0x00000300
#define BF_PINCTRL_MUXSEL9_BANK4_PIN20(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL9_BANK4_PIN20)
#define BP_PINCTRL_MUXSEL9_RSRVD0	2
#define BM_PINCTRL_MUXSEL9_RSRVD0	0x000000FC
#define BF_PINCTRL_MUXSEL9_RSRVD0(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL9_RSRVD0)
#define BP_PINCTRL_MUXSEL9_BANK4_PIN16	0
#define BM_PINCTRL_MUXSEL9_BANK4_PIN16	0x00000003
#define BF_PINCTRL_MUXSEL9_BANK4_PIN16(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL9_BANK4_PIN16)

#define HW_PINCTRL_MUXSEL10	(0x000001a0)
#define HW_PINCTRL_MUXSEL10_SET	(0x000001a4)
#define HW_PINCTRL_MUXSEL10_CLR	(0x000001a8)
#define HW_PINCTRL_MUXSEL10_TOG	(0x000001ac)

#define BP_PINCTRL_MUXSEL10_BANK5_PIN15	30
#define BM_PINCTRL_MUXSEL10_BANK5_PIN15	0xC0000000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN15(v) \
		(((v) << 30) & BM_PINCTRL_MUXSEL10_BANK5_PIN15)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN14	28
#define BM_PINCTRL_MUXSEL10_BANK5_PIN14	0x30000000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN14(v)  \
		(((v) << 28) & BM_PINCTRL_MUXSEL10_BANK5_PIN14)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN13	26
#define BM_PINCTRL_MUXSEL10_BANK5_PIN13	0x0C000000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN13(v)  \
		(((v) << 26) & BM_PINCTRL_MUXSEL10_BANK5_PIN13)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN12	24
#define BM_PINCTRL_MUXSEL10_BANK5_PIN12	0x03000000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN12(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL10_BANK5_PIN12)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN11	22
#define BM_PINCTRL_MUXSEL10_BANK5_PIN11	0x00C00000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN11(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL10_BANK5_PIN11)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN10	20
#define BM_PINCTRL_MUXSEL10_BANK5_PIN10	0x00300000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN10(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL10_BANK5_PIN10)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN09	18
#define BM_PINCTRL_MUXSEL10_BANK5_PIN09	0x000C0000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN09(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL10_BANK5_PIN09)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN08	16
#define BM_PINCTRL_MUXSEL10_BANK5_PIN08	0x00030000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN08(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL10_BANK5_PIN08)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN07	14
#define BM_PINCTRL_MUXSEL10_BANK5_PIN07	0x0000C000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN07(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL10_BANK5_PIN07)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN06	12
#define BM_PINCTRL_MUXSEL10_BANK5_PIN06	0x00003000
#define BF_PINCTRL_MUXSEL10_BANK5_PIN06(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL10_BANK5_PIN06)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN05	10
#define BM_PINCTRL_MUXSEL10_BANK5_PIN05	0x00000C00
#define BF_PINCTRL_MUXSEL10_BANK5_PIN05(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL10_BANK5_PIN05)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN04	8
#define BM_PINCTRL_MUXSEL10_BANK5_PIN04	0x00000300
#define BF_PINCTRL_MUXSEL10_BANK5_PIN04(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL10_BANK5_PIN04)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN03	6
#define BM_PINCTRL_MUXSEL10_BANK5_PIN03	0x000000C0
#define BF_PINCTRL_MUXSEL10_BANK5_PIN03(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL10_BANK5_PIN03)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN02	4
#define BM_PINCTRL_MUXSEL10_BANK5_PIN02	0x00000030
#define BF_PINCTRL_MUXSEL10_BANK5_PIN02(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL10_BANK5_PIN02)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN01	2
#define BM_PINCTRL_MUXSEL10_BANK5_PIN01	0x0000000C
#define BF_PINCTRL_MUXSEL10_BANK5_PIN01(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL10_BANK5_PIN01)
#define BP_PINCTRL_MUXSEL10_BANK5_PIN00	0
#define BM_PINCTRL_MUXSEL10_BANK5_PIN00	0x00000003
#define BF_PINCTRL_MUXSEL10_BANK5_PIN00(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL10_BANK5_PIN00)

#define HW_PINCTRL_MUXSEL11	(0x000001b0)
#define HW_PINCTRL_MUXSEL11_SET	(0x000001b4)
#define HW_PINCTRL_MUXSEL11_CLR	(0x000001b8)
#define HW_PINCTRL_MUXSEL11_TOG	(0x000001bc)

#define BP_PINCTRL_MUXSEL11_RSRVD1	22
#define BM_PINCTRL_MUXSEL11_RSRVD1	0xFFC00000
#define BF_PINCTRL_MUXSEL11_RSRVD1(v) \
		(((v) << 22) & BM_PINCTRL_MUXSEL11_RSRVD1)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN26	20
#define BM_PINCTRL_MUXSEL11_BANK5_PIN26	0x00300000
#define BF_PINCTRL_MUXSEL11_BANK5_PIN26(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL11_BANK5_PIN26)
#define BP_PINCTRL_MUXSEL11_RSRVD0	16
#define BM_PINCTRL_MUXSEL11_RSRVD0	0x000F0000
#define BF_PINCTRL_MUXSEL11_RSRVD0(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL11_RSRVD0)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN23	14
#define BM_PINCTRL_MUXSEL11_BANK5_PIN23	0x0000C000
#define BF_PINCTRL_MUXSEL11_BANK5_PIN23(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL11_BANK5_PIN23)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN22	12
#define BM_PINCTRL_MUXSEL11_BANK5_PIN22	0x00003000
#define BF_PINCTRL_MUXSEL11_BANK5_PIN22(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL11_BANK5_PIN22)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN21	10
#define BM_PINCTRL_MUXSEL11_BANK5_PIN21	0x00000C00
#define BF_PINCTRL_MUXSEL11_BANK5_PIN21(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL11_BANK5_PIN21)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN20	8
#define BM_PINCTRL_MUXSEL11_BANK5_PIN20	0x00000300
#define BF_PINCTRL_MUXSEL11_BANK5_PIN20(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL11_BANK5_PIN20)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN19	6
#define BM_PINCTRL_MUXSEL11_BANK5_PIN19	0x000000C0
#define BF_PINCTRL_MUXSEL11_BANK5_PIN19(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL11_BANK5_PIN19)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN18	4
#define BM_PINCTRL_MUXSEL11_BANK5_PIN18	0x00000030
#define BF_PINCTRL_MUXSEL11_BANK5_PIN18(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL11_BANK5_PIN18)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN17	2
#define BM_PINCTRL_MUXSEL11_BANK5_PIN17	0x0000000C
#define BF_PINCTRL_MUXSEL11_BANK5_PIN17(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL11_BANK5_PIN17)
#define BP_PINCTRL_MUXSEL11_BANK5_PIN16	0
#define BM_PINCTRL_MUXSEL11_BANK5_PIN16	0x00000003
#define BF_PINCTRL_MUXSEL11_BANK5_PIN16(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL11_BANK5_PIN16)

#define HW_PINCTRL_MUXSEL12	(0x000001c0)
#define HW_PINCTRL_MUXSEL12_SET	(0x000001c4)
#define HW_PINCTRL_MUXSEL12_CLR	(0x000001c8)
#define HW_PINCTRL_MUXSEL12_TOG	(0x000001cc)

#define BP_PINCTRL_MUXSEL12_RSRVD0	30
#define BM_PINCTRL_MUXSEL12_RSRVD0	0xC0000000
#define BF_PINCTRL_MUXSEL12_RSRVD0(v) \
		(((v) << 30) & BM_PINCTRL_MUXSEL12_RSRVD0)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN14	28
#define BM_PINCTRL_MUXSEL12_BANK6_PIN14	0x30000000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN14(v)  \
		(((v) << 28) & BM_PINCTRL_MUXSEL12_BANK6_PIN14)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN13	26
#define BM_PINCTRL_MUXSEL12_BANK6_PIN13	0x0C000000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN13(v)  \
		(((v) << 26) & BM_PINCTRL_MUXSEL12_BANK6_PIN13)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN12	24
#define BM_PINCTRL_MUXSEL12_BANK6_PIN12	0x03000000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN12(v)  \
		(((v) << 24) & BM_PINCTRL_MUXSEL12_BANK6_PIN12)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN11	22
#define BM_PINCTRL_MUXSEL12_BANK6_PIN11	0x00C00000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN11(v)  \
		(((v) << 22) & BM_PINCTRL_MUXSEL12_BANK6_PIN11)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN10	20
#define BM_PINCTRL_MUXSEL12_BANK6_PIN10	0x00300000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN10(v)  \
		(((v) << 20) & BM_PINCTRL_MUXSEL12_BANK6_PIN10)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN09	18
#define BM_PINCTRL_MUXSEL12_BANK6_PIN09	0x000C0000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN09(v)  \
		(((v) << 18) & BM_PINCTRL_MUXSEL12_BANK6_PIN09)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN08	16
#define BM_PINCTRL_MUXSEL12_BANK6_PIN08	0x00030000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN08(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL12_BANK6_PIN08)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN07	14
#define BM_PINCTRL_MUXSEL12_BANK6_PIN07	0x0000C000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN07(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL12_BANK6_PIN07)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN06	12
#define BM_PINCTRL_MUXSEL12_BANK6_PIN06	0x00003000
#define BF_PINCTRL_MUXSEL12_BANK6_PIN06(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL12_BANK6_PIN06)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN05	10
#define BM_PINCTRL_MUXSEL12_BANK6_PIN05	0x00000C00
#define BF_PINCTRL_MUXSEL12_BANK6_PIN05(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL12_BANK6_PIN05)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN04	8
#define BM_PINCTRL_MUXSEL12_BANK6_PIN04	0x00000300
#define BF_PINCTRL_MUXSEL12_BANK6_PIN04(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL12_BANK6_PIN04)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN03	6
#define BM_PINCTRL_MUXSEL12_BANK6_PIN03	0x000000C0
#define BF_PINCTRL_MUXSEL12_BANK6_PIN03(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL12_BANK6_PIN03)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN02	4
#define BM_PINCTRL_MUXSEL12_BANK6_PIN02	0x00000030
#define BF_PINCTRL_MUXSEL12_BANK6_PIN02(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL12_BANK6_PIN02)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN01	2
#define BM_PINCTRL_MUXSEL12_BANK6_PIN01	0x0000000C
#define BF_PINCTRL_MUXSEL12_BANK6_PIN01(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL12_BANK6_PIN01)
#define BP_PINCTRL_MUXSEL12_BANK6_PIN00	0
#define BM_PINCTRL_MUXSEL12_BANK6_PIN00	0x00000003
#define BF_PINCTRL_MUXSEL12_BANK6_PIN00(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL12_BANK6_PIN00)

#define HW_PINCTRL_MUXSEL13	(0x000001d0)
#define HW_PINCTRL_MUXSEL13_SET	(0x000001d4)
#define HW_PINCTRL_MUXSEL13_CLR	(0x000001d8)
#define HW_PINCTRL_MUXSEL13_TOG	(0x000001dc)

#define BP_PINCTRL_MUXSEL13_RSRVD0	18
#define BM_PINCTRL_MUXSEL13_RSRVD0	0xFFFC0000
#define BF_PINCTRL_MUXSEL13_RSRVD0(v) \
		(((v) << 18) & BM_PINCTRL_MUXSEL13_RSRVD0)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN24	16
#define BM_PINCTRL_MUXSEL13_BANK6_PIN24	0x00030000
#define BF_PINCTRL_MUXSEL13_BANK6_PIN24(v)  \
		(((v) << 16) & BM_PINCTRL_MUXSEL13_BANK6_PIN24)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN23	14
#define BM_PINCTRL_MUXSEL13_BANK6_PIN23	0x0000C000
#define BF_PINCTRL_MUXSEL13_BANK6_PIN23(v)  \
		(((v) << 14) & BM_PINCTRL_MUXSEL13_BANK6_PIN23)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN22	12
#define BM_PINCTRL_MUXSEL13_BANK6_PIN22	0x00003000
#define BF_PINCTRL_MUXSEL13_BANK6_PIN22(v)  \
		(((v) << 12) & BM_PINCTRL_MUXSEL13_BANK6_PIN22)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN21	10
#define BM_PINCTRL_MUXSEL13_BANK6_PIN21	0x00000C00
#define BF_PINCTRL_MUXSEL13_BANK6_PIN21(v)  \
		(((v) << 10) & BM_PINCTRL_MUXSEL13_BANK6_PIN21)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN20	8
#define BM_PINCTRL_MUXSEL13_BANK6_PIN20	0x00000300
#define BF_PINCTRL_MUXSEL13_BANK6_PIN20(v)  \
		(((v) << 8) & BM_PINCTRL_MUXSEL13_BANK6_PIN20)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN19	6
#define BM_PINCTRL_MUXSEL13_BANK6_PIN19	0x000000C0
#define BF_PINCTRL_MUXSEL13_BANK6_PIN19(v)  \
		(((v) << 6) & BM_PINCTRL_MUXSEL13_BANK6_PIN19)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN18	4
#define BM_PINCTRL_MUXSEL13_BANK6_PIN18	0x00000030
#define BF_PINCTRL_MUXSEL13_BANK6_PIN18(v)  \
		(((v) << 4) & BM_PINCTRL_MUXSEL13_BANK6_PIN18)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN17	2
#define BM_PINCTRL_MUXSEL13_BANK6_PIN17	0x0000000C
#define BF_PINCTRL_MUXSEL13_BANK6_PIN17(v)  \
		(((v) << 2) & BM_PINCTRL_MUXSEL13_BANK6_PIN17)
#define BP_PINCTRL_MUXSEL13_BANK6_PIN16	0
#define BM_PINCTRL_MUXSEL13_BANK6_PIN16	0x00000003
#define BF_PINCTRL_MUXSEL13_BANK6_PIN16(v)  \
		(((v) << 0) & BM_PINCTRL_MUXSEL13_BANK6_PIN16)

#define HW_PINCTRL_DRIVE0	(0x00000300)
#define HW_PINCTRL_DRIVE0_SET	(0x00000304)
#define HW_PINCTRL_DRIVE0_CLR	(0x00000308)
#define HW_PINCTRL_DRIVE0_TOG	(0x0000030c)

#define BM_PINCTRL_DRIVE0_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE0_BANK0_PIN07_V	0x40000000
#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA	28
#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA	0x30000000
#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA)
#define BM_PINCTRL_DRIVE0_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE0_BANK0_PIN06_V	0x04000000
#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA	24
#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA	0x03000000
#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA)
#define BM_PINCTRL_DRIVE0_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE0_BANK0_PIN05_V	0x00400000
#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA	20
#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA	0x00300000
#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA)
#define BM_PINCTRL_DRIVE0_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE0_BANK0_PIN04_V	0x00040000
#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA	16
#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA	0x00030000
#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA)
#define BM_PINCTRL_DRIVE0_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE0_BANK0_PIN03_V	0x00004000
#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA	12
#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA	0x00003000
#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA)
#define BM_PINCTRL_DRIVE0_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE0_BANK0_PIN02_V	0x00000400
#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA	8
#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA	0x00000300
#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA)
#define BM_PINCTRL_DRIVE0_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE0_BANK0_PIN01_V	0x00000040
#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA	4
#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA	0x00000030
#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA)
#define BM_PINCTRL_DRIVE0_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE0_BANK0_PIN00_V	0x00000004
#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA	0
#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA	0x00000003
#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA)

#define HW_PINCTRL_DRIVE1	(0x00000310)
#define HW_PINCTRL_DRIVE1_SET	(0x00000314)
#define HW_PINCTRL_DRIVE1_CLR	(0x00000318)
#define HW_PINCTRL_DRIVE1_TOG	(0x0000031c)

#define BP_PINCTRL_DRIVE1_RSRVD0	0
#define BM_PINCTRL_DRIVE1_RSRVD0	0xFFFFFFFF
#define BF_PINCTRL_DRIVE1_RSRVD0(v)	(v)

#define HW_PINCTRL_DRIVE2	(0x00000320)
#define HW_PINCTRL_DRIVE2_SET	(0x00000324)
#define HW_PINCTRL_DRIVE2_CLR	(0x00000328)
#define HW_PINCTRL_DRIVE2_TOG	(0x0000032c)

#define BM_PINCTRL_DRIVE2_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE2_BANK0_PIN23_V	0x40000000
#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA	28
#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA	0x30000000
#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA)
#define BM_PINCTRL_DRIVE2_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE2_BANK0_PIN22_V	0x04000000
#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA	24
#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA	0x03000000
#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA)
#define BM_PINCTRL_DRIVE2_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE2_BANK0_PIN21_V	0x00400000
#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA	20
#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA	0x00300000
#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA)
#define BM_PINCTRL_DRIVE2_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE2_BANK0_PIN20_V	0x00040000
#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA	16
#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA	0x00030000
#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA)
#define BM_PINCTRL_DRIVE2_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE2_BANK0_PIN19_V	0x00004000
#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA	12
#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA	0x00003000
#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA)
#define BM_PINCTRL_DRIVE2_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE2_BANK0_PIN18_V	0x00000400
#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA	8
#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA	0x00000300
#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA)
#define BM_PINCTRL_DRIVE2_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE2_BANK0_PIN17_V	0x00000040
#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA	4
#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA	0x00000030
#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA)
#define BM_PINCTRL_DRIVE2_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE2_BANK0_PIN16_V	0x00000004
#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA	0
#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA	0x00000003
#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA)

#define HW_PINCTRL_DRIVE3	(0x00000330)
#define HW_PINCTRL_DRIVE3_SET	(0x00000334)
#define HW_PINCTRL_DRIVE3_CLR	(0x00000338)
#define HW_PINCTRL_DRIVE3_TOG	(0x0000033c)

#define BP_PINCTRL_DRIVE3_RSRVD5	20
#define BM_PINCTRL_DRIVE3_RSRVD5	0xFFF00000
#define BF_PINCTRL_DRIVE3_RSRVD5(v) \
		(((v) << 20) & BM_PINCTRL_DRIVE3_RSRVD5)
#define BM_PINCTRL_DRIVE3_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE3_BANK0_PIN28_V	0x00040000
#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA	16
#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA	0x00030000
#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA)
#define BM_PINCTRL_DRIVE3_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE3_BANK0_PIN27_V	0x00004000
#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA	12
#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA	0x00003000
#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA)
#define BM_PINCTRL_DRIVE3_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE3_BANK0_PIN26_V	0x00000400
#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA	8
#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA	0x00000300
#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA)
#define BM_PINCTRL_DRIVE3_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE3_BANK0_PIN25_V	0x00000040
#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA	4
#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA	0x00000030
#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA)
#define BM_PINCTRL_DRIVE3_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE3_BANK0_PIN24_V	0x00000004
#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA	0
#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA	0x00000003
#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA)

#define HW_PINCTRL_DRIVE4	(0x00000340)
#define HW_PINCTRL_DRIVE4_SET	(0x00000344)
#define HW_PINCTRL_DRIVE4_CLR	(0x00000348)
#define HW_PINCTRL_DRIVE4_TOG	(0x0000034c)

#define BM_PINCTRL_DRIVE4_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE4_BANK1_PIN07_V	0x40000000
#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA	28
#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA	0x30000000
#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA)
#define BM_PINCTRL_DRIVE4_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE4_BANK1_PIN06_V	0x04000000
#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA	24
#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA	0x03000000
#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA)
#define BM_PINCTRL_DRIVE4_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE4_BANK1_PIN05_V	0x00400000
#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA	20
#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA	0x00300000
#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA)
#define BM_PINCTRL_DRIVE4_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE4_BANK1_PIN04_V	0x00040000
#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA	16
#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA	0x00030000
#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA)
#define BM_PINCTRL_DRIVE4_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE4_BANK1_PIN03_V	0x00004000
#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA	12
#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA	0x00003000
#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA)
#define BM_PINCTRL_DRIVE4_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE4_BANK1_PIN02_V	0x00000400
#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA	8
#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA	0x00000300
#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA)
#define BM_PINCTRL_DRIVE4_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE4_BANK1_PIN01_V	0x00000040
#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA	4
#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA	0x00000030
#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA)
#define BM_PINCTRL_DRIVE4_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE4_BANK1_PIN00_V	0x00000004
#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA	0
#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA	0x00000003
#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA)

#define HW_PINCTRL_DRIVE5	(0x00000350)
#define HW_PINCTRL_DRIVE5_SET	(0x00000354)
#define HW_PINCTRL_DRIVE5_CLR	(0x00000358)
#define HW_PINCTRL_DRIVE5_TOG	(0x0000035c)

#define BM_PINCTRL_DRIVE5_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE5_BANK1_PIN15_V	0x40000000
#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA	28
#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA	0x30000000
#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA)
#define BM_PINCTRL_DRIVE5_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE5_BANK1_PIN14_V	0x04000000
#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA	24
#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA	0x03000000
#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA)
#define BM_PINCTRL_DRIVE5_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE5_BANK1_PIN13_V	0x00400000
#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA	20
#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA	0x00300000
#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA)
#define BM_PINCTRL_DRIVE5_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE5_BANK1_PIN12_V	0x00040000
#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA	16
#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA	0x00030000
#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA)
#define BM_PINCTRL_DRIVE5_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE5_BANK1_PIN11_V	0x00004000
#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA	12
#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA	0x00003000
#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA)
#define BM_PINCTRL_DRIVE5_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE5_BANK1_PIN10_V	0x00000400
#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA	8
#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA	0x00000300
#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA)
#define BM_PINCTRL_DRIVE5_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE5_BANK1_PIN09_V	0x00000040
#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA	4
#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA	0x00000030
#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA)
#define BM_PINCTRL_DRIVE5_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE5_BANK1_PIN08_V	0x00000004
#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA	0
#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA	0x00000003
#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA)

#define HW_PINCTRL_DRIVE6	(0x00000360)
#define HW_PINCTRL_DRIVE6_SET	(0x00000364)
#define HW_PINCTRL_DRIVE6_CLR	(0x00000368)
#define HW_PINCTRL_DRIVE6_TOG	(0x0000036c)

#define BM_PINCTRL_DRIVE6_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE6_BANK1_PIN23_V	0x40000000
#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA	28
#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA	0x30000000
#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA)
#define BM_PINCTRL_DRIVE6_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE6_BANK1_PIN22_V	0x04000000
#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA	24
#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA	0x03000000
#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA)
#define BM_PINCTRL_DRIVE6_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE6_BANK1_PIN21_V	0x00400000
#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA	20
#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA	0x00300000
#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA)
#define BM_PINCTRL_DRIVE6_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE6_BANK1_PIN20_V	0x00040000
#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA	16
#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA	0x00030000
#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA)
#define BM_PINCTRL_DRIVE6_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE6_BANK1_PIN19_V	0x00004000
#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA	12
#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA	0x00003000
#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA)
#define BM_PINCTRL_DRIVE6_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE6_BANK1_PIN18_V	0x00000400
#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA	8
#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA	0x00000300
#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA)
#define BM_PINCTRL_DRIVE6_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE6_BANK1_PIN17_V	0x00000040
#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA	4
#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA	0x00000030
#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA)
#define BM_PINCTRL_DRIVE6_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE6_BANK1_PIN16_V	0x00000004
#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA	0
#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA	0x00000003
#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA)

#define HW_PINCTRL_DRIVE7	(0x00000370)
#define HW_PINCTRL_DRIVE7_SET	(0x00000374)
#define HW_PINCTRL_DRIVE7_CLR	(0x00000378)
#define HW_PINCTRL_DRIVE7_TOG	(0x0000037c)

#define BM_PINCTRL_DRIVE7_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE7_BANK1_PIN31_V	0x40000000
#define BP_PINCTRL_DRIVE7_BANK1_PIN31_MA	28
#define BM_PINCTRL_DRIVE7_BANK1_PIN31_MA	0x30000000
#define BF_PINCTRL_DRIVE7_BANK1_PIN31_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE7_BANK1_PIN31_MA)
#define BM_PINCTRL_DRIVE7_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE7_BANK1_PIN30_V	0x04000000
#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA	24
#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA	0x03000000
#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA)
#define BM_PINCTRL_DRIVE7_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE7_BANK1_PIN29_V	0x00400000
#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA	20
#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA	0x00300000
#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA)
#define BM_PINCTRL_DRIVE7_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE7_BANK1_PIN28_V	0x00040000
#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA	16
#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA	0x00030000
#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA)
#define BM_PINCTRL_DRIVE7_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE7_BANK1_PIN27_V	0x00004000
#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA	12
#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA	0x00003000
#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA)
#define BM_PINCTRL_DRIVE7_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE7_BANK1_PIN26_V	0x00000400
#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA	8
#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA	0x00000300
#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA)
#define BM_PINCTRL_DRIVE7_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE7_BANK1_PIN25_V	0x00000040
#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA	4
#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA	0x00000030
#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA)
#define BM_PINCTRL_DRIVE7_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE7_BANK1_PIN24_V	0x00000004
#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA	0
#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA	0x00000003
#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA)

#define HW_PINCTRL_DRIVE8	(0x00000380)
#define HW_PINCTRL_DRIVE8_SET	(0x00000384)
#define HW_PINCTRL_DRIVE8_CLR	(0x00000388)
#define HW_PINCTRL_DRIVE8_TOG	(0x0000038c)

#define BM_PINCTRL_DRIVE8_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE8_BANK2_PIN07_V	0x40000000
#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA	28
#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA	0x30000000
#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA)
#define BM_PINCTRL_DRIVE8_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE8_BANK2_PIN06_V	0x04000000
#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA	24
#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA	0x03000000
#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA)
#define BM_PINCTRL_DRIVE8_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE8_BANK2_PIN05_V	0x00400000
#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA	20
#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA	0x00300000
#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA)
#define BM_PINCTRL_DRIVE8_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE8_BANK2_PIN04_V	0x00040000
#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA	16
#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA	0x00030000
#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA)
#define BM_PINCTRL_DRIVE8_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE8_BANK2_PIN03_V	0x00004000
#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA	12
#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA	0x00003000
#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA)
#define BM_PINCTRL_DRIVE8_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE8_BANK2_PIN02_V	0x00000400
#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA	8
#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA	0x00000300
#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA)
#define BM_PINCTRL_DRIVE8_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE8_BANK2_PIN01_V	0x00000040
#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA	4
#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA	0x00000030
#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA)
#define BM_PINCTRL_DRIVE8_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE8_BANK2_PIN00_V	0x00000004
#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA	0
#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA	0x00000003
#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA)

#define HW_PINCTRL_DRIVE9	(0x00000390)
#define HW_PINCTRL_DRIVE9_SET	(0x00000394)
#define HW_PINCTRL_DRIVE9_CLR	(0x00000398)
#define HW_PINCTRL_DRIVE9_TOG	(0x0000039c)

#define BM_PINCTRL_DRIVE9_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V	0x40000000
#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA	28
#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA	0x30000000
#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA)
#define BM_PINCTRL_DRIVE9_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V	0x04000000
#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA	24
#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA	0x03000000
#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA)
#define BM_PINCTRL_DRIVE9_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V	0x00400000
#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA	20
#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA	0x00300000
#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA)
#define BM_PINCTRL_DRIVE9_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V	0x00040000
#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA	16
#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA	0x00030000
#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA)
#define BP_PINCTRL_DRIVE9_RSRVD3	12
#define BM_PINCTRL_DRIVE9_RSRVD3	0x0000F000
#define BF_PINCTRL_DRIVE9_RSRVD3(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE9_RSRVD3)
#define BM_PINCTRL_DRIVE9_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V	0x00000400
#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA	8
#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA	0x00000300
#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA)
#define BM_PINCTRL_DRIVE9_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V	0x00000040
#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA	4
#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA	0x00000030
#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA)
#define BM_PINCTRL_DRIVE9_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE9_BANK2_PIN08_V	0x00000004
#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA	0
#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA	0x00000003
#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA)

#define HW_PINCTRL_DRIVE10	(0x000003a0)
#define HW_PINCTRL_DRIVE10_SET	(0x000003a4)
#define HW_PINCTRL_DRIVE10_CLR	(0x000003a8)
#define HW_PINCTRL_DRIVE10_TOG	(0x000003ac)

#define BP_PINCTRL_DRIVE10_RSRVD6	24
#define BM_PINCTRL_DRIVE10_RSRVD6	0xFF000000
#define BF_PINCTRL_DRIVE10_RSRVD6(v) \
		(((v) << 24) & BM_PINCTRL_DRIVE10_RSRVD6)
#define BM_PINCTRL_DRIVE10_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V	0x00400000
#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA	20
#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA	0x00300000
#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA)
#define BM_PINCTRL_DRIVE10_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V	0x00040000
#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA	16
#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA	0x00030000
#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA)
#define BM_PINCTRL_DRIVE10_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V	0x00004000
#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA	12
#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA	0x00003000
#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA)
#define BM_PINCTRL_DRIVE10_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V	0x00000400
#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA	8
#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA	0x00000300
#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA)
#define BM_PINCTRL_DRIVE10_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V	0x00000040
#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA	4
#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA	0x00000030
#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA)
#define BM_PINCTRL_DRIVE10_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V	0x00000004
#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA	0
#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA	0x00000003
#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA)

#define HW_PINCTRL_DRIVE11	(0x000003b0)
#define HW_PINCTRL_DRIVE11_SET	(0x000003b4)
#define HW_PINCTRL_DRIVE11_CLR	(0x000003b8)
#define HW_PINCTRL_DRIVE11_TOG	(0x000003bc)

#define BP_PINCTRL_DRIVE11_RSRVD4	16
#define BM_PINCTRL_DRIVE11_RSRVD4	0xFFFF0000
#define BF_PINCTRL_DRIVE11_RSRVD4(v) \
		(((v) << 16) & BM_PINCTRL_DRIVE11_RSRVD4)
#define BM_PINCTRL_DRIVE11_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE11_BANK2_PIN27_V	0x00004000
#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA	12
#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA	0x00003000
#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA)
#define BM_PINCTRL_DRIVE11_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V	0x00000400
#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA	8
#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA	0x00000300
#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA)
#define BM_PINCTRL_DRIVE11_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V	0x00000040
#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA	4
#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA	0x00000030
#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA)
#define BM_PINCTRL_DRIVE11_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V	0x00000004
#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA	0
#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA	0x00000003
#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA)

#define HW_PINCTRL_DRIVE12	(0x000003c0)
#define HW_PINCTRL_DRIVE12_SET	(0x000003c4)
#define HW_PINCTRL_DRIVE12_CLR	(0x000003c8)
#define HW_PINCTRL_DRIVE12_TOG	(0x000003cc)

#define BM_PINCTRL_DRIVE12_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V	0x40000000
#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA	28
#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA	0x30000000
#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA)
#define BM_PINCTRL_DRIVE12_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V	0x04000000
#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA	24
#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA	0x03000000
#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA)
#define BM_PINCTRL_DRIVE12_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V	0x00400000
#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA	20
#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA	0x00300000
#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA)
#define BM_PINCTRL_DRIVE12_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V	0x00040000
#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA	16
#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA	0x00030000
#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA)
#define BM_PINCTRL_DRIVE12_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V	0x00004000
#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA	12
#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA	0x00003000
#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA)
#define BM_PINCTRL_DRIVE12_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V	0x00000400
#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA	8
#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA	0x00000300
#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA)
#define BM_PINCTRL_DRIVE12_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V	0x00000040
#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA	4
#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA	0x00000030
#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA)
#define BM_PINCTRL_DRIVE12_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V	0x00000004
#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA	0
#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA	0x00000003
#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA)

#define HW_PINCTRL_DRIVE13	(0x000003d0)
#define HW_PINCTRL_DRIVE13_SET	(0x000003d4)
#define HW_PINCTRL_DRIVE13_CLR	(0x000003d8)
#define HW_PINCTRL_DRIVE13_TOG	(0x000003dc)

#define BM_PINCTRL_DRIVE13_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V	0x40000000
#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA	28
#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA	0x30000000
#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA)
#define BM_PINCTRL_DRIVE13_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V	0x04000000
#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA	24
#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA	0x03000000
#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA)
#define BM_PINCTRL_DRIVE13_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V	0x00400000
#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA	20
#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA	0x00300000
#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA)
#define BM_PINCTRL_DRIVE13_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V	0x00040000
#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA	16
#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA	0x00030000
#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA)
#define BM_PINCTRL_DRIVE13_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V	0x00004000
#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA	12
#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA	0x00003000
#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA)
#define BM_PINCTRL_DRIVE13_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V	0x00000400
#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA	8
#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA	0x00000300
#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA)
#define BM_PINCTRL_DRIVE13_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V	0x00000040
#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA	4
#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA	0x00000030
#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA)
#define BM_PINCTRL_DRIVE13_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V	0x00000004
#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA	0
#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA	0x00000003
#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA)

#define HW_PINCTRL_DRIVE14	(0x000003e0)
#define HW_PINCTRL_DRIVE14_SET	(0x000003e4)
#define HW_PINCTRL_DRIVE14_CLR	(0x000003e8)
#define HW_PINCTRL_DRIVE14_TOG	(0x000003ec)

#define BM_PINCTRL_DRIVE14_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE14_BANK3_PIN23_V	0x40000000
#define BP_PINCTRL_DRIVE14_BANK3_PIN23_MA	28
#define BM_PINCTRL_DRIVE14_BANK3_PIN23_MA	0x30000000
#define BF_PINCTRL_DRIVE14_BANK3_PIN23_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE14_BANK3_PIN23_MA)
#define BM_PINCTRL_DRIVE14_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE14_BANK3_PIN22_V	0x04000000
#define BP_PINCTRL_DRIVE14_BANK3_PIN22_MA	24
#define BM_PINCTRL_DRIVE14_BANK3_PIN22_MA	0x03000000
#define BF_PINCTRL_DRIVE14_BANK3_PIN22_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE14_BANK3_PIN22_MA)
#define BM_PINCTRL_DRIVE14_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V	0x00400000
#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA	20
#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA	0x00300000
#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA)
#define BM_PINCTRL_DRIVE14_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V	0x00040000
#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA	16
#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA	0x00030000
#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA)
#define BP_PINCTRL_DRIVE14_RSRVD3	12
#define BM_PINCTRL_DRIVE14_RSRVD3	0x0000F000
#define BF_PINCTRL_DRIVE14_RSRVD3(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE14_RSRVD3)
#define BM_PINCTRL_DRIVE14_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V	0x00000400
#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA	8
#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA	0x00000300
#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA)
#define BM_PINCTRL_DRIVE14_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V	0x00000040
#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA	4
#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA	0x00000030
#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA)
#define BM_PINCTRL_DRIVE14_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V	0x00000004
#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA	0
#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA	0x00000003
#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA)

#define HW_PINCTRL_DRIVE15	(0x000003f0)
#define HW_PINCTRL_DRIVE15_SET	(0x000003f4)
#define HW_PINCTRL_DRIVE15_CLR	(0x000003f8)
#define HW_PINCTRL_DRIVE15_TOG	(0x000003fc)

#define BP_PINCTRL_DRIVE15_RSRVD7	28
#define BM_PINCTRL_DRIVE15_RSRVD7	0xF0000000
#define BF_PINCTRL_DRIVE15_RSRVD7(v) \
		(((v) << 28) & BM_PINCTRL_DRIVE15_RSRVD7)
#define BM_PINCTRL_DRIVE15_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE15_BANK3_PIN30_V	0x04000000
#define BP_PINCTRL_DRIVE15_BANK3_PIN30_MA	24
#define BM_PINCTRL_DRIVE15_BANK3_PIN30_MA	0x03000000
#define BF_PINCTRL_DRIVE15_BANK3_PIN30_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE15_BANK3_PIN30_MA)
#define BM_PINCTRL_DRIVE15_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE15_BANK3_PIN29_V	0x00400000
#define BP_PINCTRL_DRIVE15_BANK3_PIN29_MA	20
#define BM_PINCTRL_DRIVE15_BANK3_PIN29_MA	0x00300000
#define BF_PINCTRL_DRIVE15_BANK3_PIN29_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE15_BANK3_PIN29_MA)
#define BM_PINCTRL_DRIVE15_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE15_BANK3_PIN28_V	0x00040000
#define BP_PINCTRL_DRIVE15_BANK3_PIN28_MA	16
#define BM_PINCTRL_DRIVE15_BANK3_PIN28_MA	0x00030000
#define BF_PINCTRL_DRIVE15_BANK3_PIN28_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE15_BANK3_PIN28_MA)
#define BM_PINCTRL_DRIVE15_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE15_BANK3_PIN27_V	0x00004000
#define BP_PINCTRL_DRIVE15_BANK3_PIN27_MA	12
#define BM_PINCTRL_DRIVE15_BANK3_PIN27_MA	0x00003000
#define BF_PINCTRL_DRIVE15_BANK3_PIN27_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE15_BANK3_PIN27_MA)
#define BM_PINCTRL_DRIVE15_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE15_BANK3_PIN26_V	0x00000400
#define BP_PINCTRL_DRIVE15_BANK3_PIN26_MA	8
#define BM_PINCTRL_DRIVE15_BANK3_PIN26_MA	0x00000300
#define BF_PINCTRL_DRIVE15_BANK3_PIN26_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE15_BANK3_PIN26_MA)
#define BM_PINCTRL_DRIVE15_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE15_BANK3_PIN25_V	0x00000040
#define BP_PINCTRL_DRIVE15_BANK3_PIN25_MA	4
#define BM_PINCTRL_DRIVE15_BANK3_PIN25_MA	0x00000030
#define BF_PINCTRL_DRIVE15_BANK3_PIN25_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE15_BANK3_PIN25_MA)
#define BM_PINCTRL_DRIVE15_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE15_BANK3_PIN24_V	0x00000004
#define BP_PINCTRL_DRIVE15_BANK3_PIN24_MA	0
#define BM_PINCTRL_DRIVE15_BANK3_PIN24_MA	0x00000003
#define BF_PINCTRL_DRIVE15_BANK3_PIN24_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE15_BANK3_PIN24_MA)

#define HW_PINCTRL_DRIVE16	(0x00000400)
#define HW_PINCTRL_DRIVE16_SET	(0x00000404)
#define HW_PINCTRL_DRIVE16_CLR	(0x00000408)
#define HW_PINCTRL_DRIVE16_TOG	(0x0000040c)

#define BM_PINCTRL_DRIVE16_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE16_BANK4_PIN07_V	0x40000000
#define BP_PINCTRL_DRIVE16_BANK4_PIN07_MA	28
#define BM_PINCTRL_DRIVE16_BANK4_PIN07_MA	0x30000000
#define BF_PINCTRL_DRIVE16_BANK4_PIN07_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE16_BANK4_PIN07_MA)
#define BM_PINCTRL_DRIVE16_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE16_BANK4_PIN06_V	0x04000000
#define BP_PINCTRL_DRIVE16_BANK4_PIN06_MA	24
#define BM_PINCTRL_DRIVE16_BANK4_PIN06_MA	0x03000000
#define BF_PINCTRL_DRIVE16_BANK4_PIN06_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE16_BANK4_PIN06_MA)
#define BM_PINCTRL_DRIVE16_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE16_BANK4_PIN05_V	0x00400000
#define BP_PINCTRL_DRIVE16_BANK4_PIN05_MA	20
#define BM_PINCTRL_DRIVE16_BANK4_PIN05_MA	0x00300000
#define BF_PINCTRL_DRIVE16_BANK4_PIN05_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE16_BANK4_PIN05_MA)
#define BM_PINCTRL_DRIVE16_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE16_BANK4_PIN04_V	0x00040000
#define BP_PINCTRL_DRIVE16_BANK4_PIN04_MA	16
#define BM_PINCTRL_DRIVE16_BANK4_PIN04_MA	0x00030000
#define BF_PINCTRL_DRIVE16_BANK4_PIN04_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE16_BANK4_PIN04_MA)
#define BM_PINCTRL_DRIVE16_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE16_BANK4_PIN03_V	0x00004000
#define BP_PINCTRL_DRIVE16_BANK4_PIN03_MA	12
#define BM_PINCTRL_DRIVE16_BANK4_PIN03_MA	0x00003000
#define BF_PINCTRL_DRIVE16_BANK4_PIN03_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE16_BANK4_PIN03_MA)
#define BM_PINCTRL_DRIVE16_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE16_BANK4_PIN02_V	0x00000400
#define BP_PINCTRL_DRIVE16_BANK4_PIN02_MA	8
#define BM_PINCTRL_DRIVE16_BANK4_PIN02_MA	0x00000300
#define BF_PINCTRL_DRIVE16_BANK4_PIN02_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE16_BANK4_PIN02_MA)
#define BM_PINCTRL_DRIVE16_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE16_BANK4_PIN01_V	0x00000040
#define BP_PINCTRL_DRIVE16_BANK4_PIN01_MA	4
#define BM_PINCTRL_DRIVE16_BANK4_PIN01_MA	0x00000030
#define BF_PINCTRL_DRIVE16_BANK4_PIN01_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE16_BANK4_PIN01_MA)
#define BM_PINCTRL_DRIVE16_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE16_BANK4_PIN00_V	0x00000004
#define BP_PINCTRL_DRIVE16_BANK4_PIN00_MA	0
#define BM_PINCTRL_DRIVE16_BANK4_PIN00_MA	0x00000003
#define BF_PINCTRL_DRIVE16_BANK4_PIN00_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE16_BANK4_PIN00_MA)

#define HW_PINCTRL_DRIVE17	(0x00000410)
#define HW_PINCTRL_DRIVE17_SET	(0x00000414)
#define HW_PINCTRL_DRIVE17_CLR	(0x00000418)
#define HW_PINCTRL_DRIVE17_TOG	(0x0000041c)

#define BM_PINCTRL_DRIVE17_RSRVD7	0x80000000
#define BM_PINCTRL_DRIVE17_BANK4_PIN15_V	0x40000000
#define BP_PINCTRL_DRIVE17_BANK4_PIN15_MA	28
#define BM_PINCTRL_DRIVE17_BANK4_PIN15_MA	0x30000000
#define BF_PINCTRL_DRIVE17_BANK4_PIN15_MA(v)  \
		(((v) << 28) & BM_PINCTRL_DRIVE17_BANK4_PIN15_MA)
#define BM_PINCTRL_DRIVE17_RSRVD6	0x08000000
#define BM_PINCTRL_DRIVE17_BANK4_PIN14_V	0x04000000
#define BP_PINCTRL_DRIVE17_BANK4_PIN14_MA	24
#define BM_PINCTRL_DRIVE17_BANK4_PIN14_MA	0x03000000
#define BF_PINCTRL_DRIVE17_BANK4_PIN14_MA(v)  \
		(((v) << 24) & BM_PINCTRL_DRIVE17_BANK4_PIN14_MA)
#define BM_PINCTRL_DRIVE17_RSRVD5	0x00800000
#define BM_PINCTRL_DRIVE17_BANK4_PIN13_V	0x00400000
#define BP_PINCTRL_DRIVE17_BANK4_PIN13_MA	20
#define BM_PINCTRL_DRIVE17_BANK4_PIN13_MA	0x00300000
#define BF_PINCTRL_DRIVE17_BANK4_PIN13_MA(v)  \
		(((v) << 20) & BM_PINCTRL_DRIVE17_BANK4_PIN13_MA)
#define BM_PINCTRL_DRIVE17_RSRVD4	0x00080000
#define BM_PINCTRL_DRIVE17_BANK4_PIN12_V	0x00040000
#define BP_PINCTRL_DRIVE17_BANK4_PIN12_MA	16
#define BM_PINCTRL_DRIVE17_BANK4_PIN12_MA	0x00030000
#define BF_PINCTRL_DRIVE17_BANK4_PIN12_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE17_BANK4_PIN12_MA)
#define BM_PINCTRL_DRIVE17_RSRVD3	0x00008000
#define BM_PINCTRL_DRIVE17_BANK4_PIN11_V	0x00004000
#define BP_PINCTRL_DRIVE17_BANK4_PIN11_MA	12
#define BM_PINCTRL_DRIVE17_BANK4_PIN11_MA	0x00003000
#define BF_PINCTRL_DRIVE17_BANK4_PIN11_MA(v)  \
		(((v) << 12) & BM_PINCTRL_DRIVE17_BANK4_PIN11_MA)
#define BM_PINCTRL_DRIVE17_RSRVD2	0x00000800
#define BM_PINCTRL_DRIVE17_BANK4_PIN10_V	0x00000400
#define BP_PINCTRL_DRIVE17_BANK4_PIN10_MA	8
#define BM_PINCTRL_DRIVE17_BANK4_PIN10_MA	0x00000300
#define BF_PINCTRL_DRIVE17_BANK4_PIN10_MA(v)  \
		(((v) << 8) & BM_PINCTRL_DRIVE17_BANK4_PIN10_MA)
#define BM_PINCTRL_DRIVE17_RSRVD1	0x00000080
#define BM_PINCTRL_DRIVE17_BANK4_PIN09_V	0x00000040
#define BP_PINCTRL_DRIVE17_BANK4_PIN09_MA	4
#define BM_PINCTRL_DRIVE17_BANK4_PIN09_MA	0x00000030
#define BF_PINCTRL_DRIVE17_BANK4_PIN09_MA(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE17_BANK4_PIN09_MA)
#define BM_PINCTRL_DRIVE17_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE17_BANK4_PIN08_V	0x00000004
#define BP_PINCTRL_DRIVE17_BANK4_PIN08_MA	0
#define BM_PINCTRL_DRIVE17_BANK4_PIN08_MA	0x00000003
#define BF_PINCTRL_DRIVE17_BANK4_PIN08_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE17_BANK4_PIN08_MA)

#define HW_PINCTRL_DRIVE18	(0x00000420)
#define HW_PINCTRL_DRIVE18_SET	(0x00000424)
#define HW_PINCTRL_DRIVE18_CLR	(0x00000428)
#define HW_PINCTRL_DRIVE18_TOG	(0x0000042c)

#define BP_PINCTRL_DRIVE18_RSRVD3	20
#define BM_PINCTRL_DRIVE18_RSRVD3	0xFFF00000
#define BF_PINCTRL_DRIVE18_RSRVD3(v) \
		(((v) << 20) & BM_PINCTRL_DRIVE18_RSRVD3)
#define BM_PINCTRL_DRIVE18_RSRVD2	0x00080000
#define BM_PINCTRL_DRIVE18_BANK4_PIN20_V	0x00040000
#define BP_PINCTRL_DRIVE18_BANK4_PIN20_MA	16
#define BM_PINCTRL_DRIVE18_BANK4_PIN20_MA	0x00030000
#define BF_PINCTRL_DRIVE18_BANK4_PIN20_MA(v)  \
		(((v) << 16) & BM_PINCTRL_DRIVE18_BANK4_PIN20_MA)
#define BP_PINCTRL_DRIVE18_RSRVD1	4
#define BM_PINCTRL_DRIVE18_RSRVD1	0x0000FFF0
#define BF_PINCTRL_DRIVE18_RSRVD1(v)  \
		(((v) << 4) & BM_PINCTRL_DRIVE18_RSRVD1)
#define BM_PINCTRL_DRIVE18_RSRVD0	0x00000008
#define BM_PINCTRL_DRIVE18_BANK4_PIN16_V	0x00000004
#define BP_PINCTRL_DRIVE18_BANK4_PIN16_MA	0
#define BM_PINCTRL_DRIVE18_BANK4_PIN16_MA	0x00000003
#define BF_PINCTRL_DRIVE18_BANK4_PIN16_MA(v)  \
		(((v) << 0) & BM_PINCTRL_DRIVE18_BANK4_PIN16_MA)

#define HW_PINCTRL_DRIVE19	(0x00000430)
#define HW_PINCTRL_DRIVE19_SET	(0x00000434)
#define HW_PINCTRL_DRIVE19_CLR	(0x00000438)
#define HW_PINCTRL_DRIVE19_TOG	(0x0000043c)

#define BP_PINCTRL_DRIVE19_RSRVD0	0
#define BM_PINCTRL_DRIVE19_RSRVD0	0xFFFFFFFF
#define BF_PINCTRL_DRIVE19_RSRVD0(v)	(v)

#define HW_PINCTRL_PULL0	(0x00000600)
#define HW_PINCTRL_PULL0_SET	(0x00000604)
#define HW_PINCTRL_PULL0_CLR	(0x00000608)
#define HW_PINCTRL_PULL0_TOG	(0x0000060c)

#define BP_PINCTRL_PULL0_RSRVD1	29
#define BM_PINCTRL_PULL0_RSRVD1	0xE0000000
#define BF_PINCTRL_PULL0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_PULL0_RSRVD1)
#define BM_PINCTRL_PULL0_BANK0_PIN28	0x10000000
#define BM_PINCTRL_PULL0_BANK0_PIN27	0x08000000
#define BM_PINCTRL_PULL0_BANK0_PIN26	0x04000000
#define BM_PINCTRL_PULL0_BANK0_PIN25	0x02000000
#define BM_PINCTRL_PULL0_BANK0_PIN24	0x01000000
#define BM_PINCTRL_PULL0_BANK0_PIN23	0x00800000
#define BM_PINCTRL_PULL0_BANK0_PIN22	0x00400000
#define BM_PINCTRL_PULL0_BANK0_PIN21	0x00200000
#define BM_PINCTRL_PULL0_BANK0_PIN20	0x00100000
#define BM_PINCTRL_PULL0_BANK0_PIN19	0x00080000
#define BM_PINCTRL_PULL0_BANK0_PIN18	0x00040000
#define BM_PINCTRL_PULL0_BANK0_PIN17	0x00020000
#define BM_PINCTRL_PULL0_BANK0_PIN16	0x00010000
#define BP_PINCTRL_PULL0_RSRVD0	8
#define BM_PINCTRL_PULL0_RSRVD0	0x0000FF00
#define BF_PINCTRL_PULL0_RSRVD0(v)  \
		(((v) << 8) & BM_PINCTRL_PULL0_RSRVD0)
#define BM_PINCTRL_PULL0_BANK0_PIN07	0x00000080
#define BM_PINCTRL_PULL0_BANK0_PIN06	0x00000040
#define BM_PINCTRL_PULL0_BANK0_PIN05	0x00000020
#define BM_PINCTRL_PULL0_BANK0_PIN04	0x00000010
#define BM_PINCTRL_PULL0_BANK0_PIN03	0x00000008
#define BM_PINCTRL_PULL0_BANK0_PIN02	0x00000004
#define BM_PINCTRL_PULL0_BANK0_PIN01	0x00000002
#define BM_PINCTRL_PULL0_BANK0_PIN00	0x00000001

#define HW_PINCTRL_PULL1	(0x00000610)
#define HW_PINCTRL_PULL1_SET	(0x00000614)
#define HW_PINCTRL_PULL1_CLR	(0x00000618)
#define HW_PINCTRL_PULL1_TOG	(0x0000061c)

#define BM_PINCTRL_PULL1_BANK1_PIN31	0x80000000
#define BM_PINCTRL_PULL1_BANK1_PIN30	0x40000000
#define BM_PINCTRL_PULL1_BANK1_PIN29	0x20000000
#define BM_PINCTRL_PULL1_BANK1_PIN28	0x10000000
#define BM_PINCTRL_PULL1_BANK1_PIN27	0x08000000
#define BM_PINCTRL_PULL1_BANK1_PIN26	0x04000000
#define BM_PINCTRL_PULL1_BANK1_PIN25	0x02000000
#define BM_PINCTRL_PULL1_BANK1_PIN24	0x01000000
#define BM_PINCTRL_PULL1_BANK1_PIN23	0x00800000
#define BM_PINCTRL_PULL1_BANK1_PIN22	0x00400000
#define BM_PINCTRL_PULL1_BANK1_PIN21	0x00200000
#define BM_PINCTRL_PULL1_BANK1_PIN20	0x00100000
#define BM_PINCTRL_PULL1_BANK1_PIN19	0x00080000
#define BM_PINCTRL_PULL1_BANK1_PIN18	0x00040000
#define BM_PINCTRL_PULL1_BANK1_PIN17	0x00020000
#define BM_PINCTRL_PULL1_BANK1_PIN16	0x00010000
#define BM_PINCTRL_PULL1_BANK1_PIN15	0x00008000
#define BM_PINCTRL_PULL1_BANK1_PIN14	0x00004000
#define BM_PINCTRL_PULL1_BANK1_PIN13	0x00002000
#define BM_PINCTRL_PULL1_BANK1_PIN12	0x00001000
#define BM_PINCTRL_PULL1_BANK1_PIN11	0x00000800
#define BM_PINCTRL_PULL1_BANK1_PIN10	0x00000400
#define BM_PINCTRL_PULL1_BANK1_PIN09	0x00000200
#define BM_PINCTRL_PULL1_BANK1_PIN08	0x00000100
#define BM_PINCTRL_PULL1_BANK1_PIN07	0x00000080
#define BM_PINCTRL_PULL1_BANK1_PIN06	0x00000040
#define BM_PINCTRL_PULL1_BANK1_PIN05	0x00000020
#define BM_PINCTRL_PULL1_BANK1_PIN04	0x00000010
#define BM_PINCTRL_PULL1_BANK1_PIN03	0x00000008
#define BM_PINCTRL_PULL1_BANK1_PIN02	0x00000004
#define BM_PINCTRL_PULL1_BANK1_PIN01	0x00000002
#define BM_PINCTRL_PULL1_BANK1_PIN00	0x00000001

#define HW_PINCTRL_PULL2	(0x00000620)
#define HW_PINCTRL_PULL2_SET	(0x00000624)
#define HW_PINCTRL_PULL2_CLR	(0x00000628)
#define HW_PINCTRL_PULL2_TOG	(0x0000062c)

#define BP_PINCTRL_PULL2_RSRVD2	28
#define BM_PINCTRL_PULL2_RSRVD2	0xF0000000
#define BF_PINCTRL_PULL2_RSRVD2(v) \
		(((v) << 28) & BM_PINCTRL_PULL2_RSRVD2)
#define BM_PINCTRL_PULL2_BANK2_PIN27	0x08000000
#define BM_PINCTRL_PULL2_BANK2_PIN26	0x04000000
#define BM_PINCTRL_PULL2_BANK2_PIN25	0x02000000
#define BM_PINCTRL_PULL2_BANK2_PIN24	0x01000000
#define BP_PINCTRL_PULL2_RSRVD1	22
#define BM_PINCTRL_PULL2_RSRVD1	0x00C00000
#define BF_PINCTRL_PULL2_RSRVD1(v)  \
		(((v) << 22) & BM_PINCTRL_PULL2_RSRVD1)
#define BM_PINCTRL_PULL2_BANK2_PIN21	0x00200000
#define BM_PINCTRL_PULL2_BANK2_PIN20	0x00100000
#define BM_PINCTRL_PULL2_BANK2_PIN19	0x00080000
#define BM_PINCTRL_PULL2_BANK2_PIN18	0x00040000
#define BM_PINCTRL_PULL2_BANK2_PIN17	0x00020000
#define BM_PINCTRL_PULL2_BANK2_PIN16	0x00010000
#define BM_PINCTRL_PULL2_BANK2_PIN15	0x00008000
#define BM_PINCTRL_PULL2_BANK2_PIN14	0x00004000
#define BM_PINCTRL_PULL2_BANK2_PIN13	0x00002000
#define BM_PINCTRL_PULL2_BANK2_PIN12	0x00001000
#define BM_PINCTRL_PULL2_RSRVD0	0x00000800
#define BM_PINCTRL_PULL2_BANK2_PIN10	0x00000400
#define BM_PINCTRL_PULL2_BANK2_PIN09	0x00000200
#define BM_PINCTRL_PULL2_BANK2_PIN08	0x00000100
#define BM_PINCTRL_PULL2_BANK2_PIN07	0x00000080
#define BM_PINCTRL_PULL2_BANK2_PIN06	0x00000040
#define BM_PINCTRL_PULL2_BANK2_PIN05	0x00000020
#define BM_PINCTRL_PULL2_BANK2_PIN04	0x00000010
#define BM_PINCTRL_PULL2_BANK2_PIN03	0x00000008
#define BM_PINCTRL_PULL2_BANK2_PIN02	0x00000004
#define BM_PINCTRL_PULL2_BANK2_PIN01	0x00000002
#define BM_PINCTRL_PULL2_BANK2_PIN00	0x00000001

#define HW_PINCTRL_PULL3	(0x00000630)
#define HW_PINCTRL_PULL3_SET	(0x00000634)
#define HW_PINCTRL_PULL3_CLR	(0x00000638)
#define HW_PINCTRL_PULL3_TOG	(0x0000063c)

#define BM_PINCTRL_PULL3_RSRVD1	0x80000000
#define BM_PINCTRL_PULL3_BANK3_PIN30	0x40000000
#define BM_PINCTRL_PULL3_BANK3_PIN29	0x20000000
#define BM_PINCTRL_PULL3_BANK3_PIN28	0x10000000
#define BM_PINCTRL_PULL3_BANK3_PIN27	0x08000000
#define BM_PINCTRL_PULL3_BANK3_PIN26	0x04000000
#define BM_PINCTRL_PULL3_BANK3_PIN25	0x02000000
#define BM_PINCTRL_PULL3_BANK3_PIN24	0x01000000
#define BM_PINCTRL_PULL3_BANK3_PIN23	0x00800000
#define BM_PINCTRL_PULL3_BANK3_PIN22	0x00400000
#define BM_PINCTRL_PULL3_BANK3_PIN21	0x00200000
#define BM_PINCTRL_PULL3_BANK3_PIN20	0x00100000
#define BM_PINCTRL_PULL3_RSRVD0	0x00080000
#define BM_PINCTRL_PULL3_BANK3_PIN18	0x00040000
#define BM_PINCTRL_PULL3_BANK3_PIN17	0x00020000
#define BM_PINCTRL_PULL3_BANK3_PIN16	0x00010000
#define BM_PINCTRL_PULL3_BANK3_PIN15	0x00008000
#define BM_PINCTRL_PULL3_BANK3_PIN14	0x00004000
#define BM_PINCTRL_PULL3_BANK3_PIN13	0x00002000
#define BM_PINCTRL_PULL3_BANK3_PIN12	0x00001000
#define BM_PINCTRL_PULL3_BANK3_PIN11	0x00000800
#define BM_PINCTRL_PULL3_BANK3_PIN10	0x00000400
#define BM_PINCTRL_PULL3_BANK3_PIN09	0x00000200
#define BM_PINCTRL_PULL3_BANK3_PIN08	0x00000100
#define BM_PINCTRL_PULL3_BANK3_PIN07	0x00000080
#define BM_PINCTRL_PULL3_BANK3_PIN06	0x00000040
#define BM_PINCTRL_PULL3_BANK3_PIN05	0x00000020
#define BM_PINCTRL_PULL3_BANK3_PIN04	0x00000010
#define BM_PINCTRL_PULL3_BANK3_PIN03	0x00000008
#define BM_PINCTRL_PULL3_BANK3_PIN02	0x00000004
#define BM_PINCTRL_PULL3_BANK3_PIN01	0x00000002
#define BM_PINCTRL_PULL3_BANK3_PIN00	0x00000001

#define HW_PINCTRL_PULL4	(0x00000640)
#define HW_PINCTRL_PULL4_SET	(0x00000644)
#define HW_PINCTRL_PULL4_CLR	(0x00000648)
#define HW_PINCTRL_PULL4_TOG	(0x0000064c)

#define BP_PINCTRL_PULL4_RSRVD1	21
#define BM_PINCTRL_PULL4_RSRVD1	0xFFE00000
#define BF_PINCTRL_PULL4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_PULL4_RSRVD1)
#define BM_PINCTRL_PULL4_BANK4_PIN20	0x00100000
#define BP_PINCTRL_PULL4_RSRVD0	17
#define BM_PINCTRL_PULL4_RSRVD0	0x000E0000
#define BF_PINCTRL_PULL4_RSRVD0(v)  \
		(((v) << 17) & BM_PINCTRL_PULL4_RSRVD0)
#define BM_PINCTRL_PULL4_BANK4_PIN16	0x00010000
#define BM_PINCTRL_PULL4_BANK4_PIN15	0x00008000
#define BM_PINCTRL_PULL4_BANK4_PIN14	0x00004000
#define BM_PINCTRL_PULL4_BANK4_PIN13	0x00002000
#define BM_PINCTRL_PULL4_BANK4_PIN12	0x00001000
#define BM_PINCTRL_PULL4_BANK4_PIN11	0x00000800
#define BM_PINCTRL_PULL4_BANK4_PIN10	0x00000400
#define BM_PINCTRL_PULL4_BANK4_PIN09	0x00000200
#define BM_PINCTRL_PULL4_BANK4_PIN08	0x00000100
#define BM_PINCTRL_PULL4_BANK4_PIN07	0x00000080
#define BM_PINCTRL_PULL4_BANK4_PIN06	0x00000040
#define BM_PINCTRL_PULL4_BANK4_PIN05	0x00000020
#define BM_PINCTRL_PULL4_BANK4_PIN04	0x00000010
#define BM_PINCTRL_PULL4_BANK4_PIN03	0x00000008
#define BM_PINCTRL_PULL4_BANK4_PIN02	0x00000004
#define BM_PINCTRL_PULL4_BANK4_PIN01	0x00000002
#define BM_PINCTRL_PULL4_BANK4_PIN00	0x00000001

#define HW_PINCTRL_PULL5	(0x00000650)
#define HW_PINCTRL_PULL5_SET	(0x00000654)
#define HW_PINCTRL_PULL5_CLR	(0x00000658)
#define HW_PINCTRL_PULL5_TOG	(0x0000065c)

#define BP_PINCTRL_PULL5_RSRVD1	27
#define BM_PINCTRL_PULL5_RSRVD1	0xF8000000
#define BF_PINCTRL_PULL5_RSRVD1(v) \
		(((v) << 27) & BM_PINCTRL_PULL5_RSRVD1)
#define BM_PINCTRL_PULL5_BANK5_PIN26	0x04000000
#define BP_PINCTRL_PULL5_RSRVD0	24
#define BM_PINCTRL_PULL5_RSRVD0	0x03000000
#define BF_PINCTRL_PULL5_RSRVD0(v)  \
		(((v) << 24) & BM_PINCTRL_PULL5_RSRVD0)
#define BM_PINCTRL_PULL5_BANK5_PIN23	0x00800000
#define BM_PINCTRL_PULL5_BANK5_PIN22	0x00400000
#define BM_PINCTRL_PULL5_BANK5_PIN21	0x00200000
#define BM_PINCTRL_PULL5_BANK5_PIN20	0x00100000
#define BM_PINCTRL_PULL5_BANK5_PIN19	0x00080000
#define BM_PINCTRL_PULL5_BANK5_PIN18	0x00040000
#define BM_PINCTRL_PULL5_BANK5_PIN17	0x00020000
#define BM_PINCTRL_PULL5_BANK5_PIN16	0x00010000
#define BM_PINCTRL_PULL5_BANK5_PIN15	0x00008000
#define BM_PINCTRL_PULL5_BANK5_PIN14	0x00004000
#define BM_PINCTRL_PULL5_BANK5_PIN13	0x00002000
#define BM_PINCTRL_PULL5_BANK5_PIN12	0x00001000
#define BM_PINCTRL_PULL5_BANK5_PIN11	0x00000800
#define BM_PINCTRL_PULL5_BANK5_PIN10	0x00000400
#define BM_PINCTRL_PULL5_BANK5_PIN09	0x00000200
#define BM_PINCTRL_PULL5_BANK5_PIN08	0x00000100
#define BM_PINCTRL_PULL5_BANK5_PIN07	0x00000080
#define BM_PINCTRL_PULL5_BANK5_PIN06	0x00000040
#define BM_PINCTRL_PULL5_BANK5_PIN05	0x00000020
#define BM_PINCTRL_PULL5_BANK5_PIN04	0x00000010
#define BM_PINCTRL_PULL5_BANK5_PIN03	0x00000008
#define BM_PINCTRL_PULL5_BANK5_PIN02	0x00000004
#define BM_PINCTRL_PULL5_BANK5_PIN01	0x00000002
#define BM_PINCTRL_PULL5_BANK5_PIN00	0x00000001

#define HW_PINCTRL_PULL6	(0x00000660)
#define HW_PINCTRL_PULL6_SET	(0x00000664)
#define HW_PINCTRL_PULL6_CLR	(0x00000668)
#define HW_PINCTRL_PULL6_TOG	(0x0000066c)

#define BP_PINCTRL_PULL6_RSRVD1	25
#define BM_PINCTRL_PULL6_RSRVD1	0xFE000000
#define BF_PINCTRL_PULL6_RSRVD1(v) \
		(((v) << 25) & BM_PINCTRL_PULL6_RSRVD1)
#define BM_PINCTRL_PULL6_BANK6_PIN24	0x01000000
#define BM_PINCTRL_PULL6_BANK6_PIN23	0x00800000
#define BM_PINCTRL_PULL6_BANK6_PIN22	0x00400000
#define BM_PINCTRL_PULL6_BANK6_PIN21	0x00200000
#define BM_PINCTRL_PULL6_BANK6_PIN20	0x00100000
#define BM_PINCTRL_PULL6_BANK6_PIN19	0x00080000
#define BM_PINCTRL_PULL6_BANK6_PIN18	0x00040000
#define BM_PINCTRL_PULL6_BANK6_PIN17	0x00020000
#define BM_PINCTRL_PULL6_BANK6_PIN16	0x00010000
#define BM_PINCTRL_PULL6_RSRVD0	0x00008000
#define BM_PINCTRL_PULL6_BANK6_PIN14	0x00004000
#define BM_PINCTRL_PULL6_BANK6_PIN13	0x00002000
#define BM_PINCTRL_PULL6_BANK6_PIN12	0x00001000
#define BM_PINCTRL_PULL6_BANK6_PIN11	0x00000800
#define BM_PINCTRL_PULL6_BANK6_PIN10	0x00000400
#define BM_PINCTRL_PULL6_BANK6_PIN09	0x00000200
#define BM_PINCTRL_PULL6_BANK6_PIN08	0x00000100
#define BM_PINCTRL_PULL6_BANK6_PIN07	0x00000080
#define BM_PINCTRL_PULL6_BANK6_PIN06	0x00000040
#define BM_PINCTRL_PULL6_BANK6_PIN05	0x00000020
#define BM_PINCTRL_PULL6_BANK6_PIN04	0x00000010
#define BM_PINCTRL_PULL6_BANK6_PIN03	0x00000008
#define BM_PINCTRL_PULL6_BANK6_PIN02	0x00000004
#define BM_PINCTRL_PULL6_BANK6_PIN01	0x00000002
#define BM_PINCTRL_PULL6_BANK6_PIN00	0x00000001

#define HW_PINCTRL_DOUT0	(0x00000700)
#define HW_PINCTRL_DOUT0_SET	(0x00000704)
#define HW_PINCTRL_DOUT0_CLR	(0x00000708)
#define HW_PINCTRL_DOUT0_TOG	(0x0000070c)

#define BP_PINCTRL_DOUT0_RSRVD1	29
#define BM_PINCTRL_DOUT0_RSRVD1	0xE0000000
#define BF_PINCTRL_DOUT0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_DOUT0_RSRVD1)
#define BP_PINCTRL_DOUT0_DOUT	0
#define BM_PINCTRL_DOUT0_DOUT	0x1FFFFFFF
#define BF_PINCTRL_DOUT0_DOUT(v)  \
		(((v) << 0) & BM_PINCTRL_DOUT0_DOUT)

#define HW_PINCTRL_DOUT1	(0x00000710)
#define HW_PINCTRL_DOUT1_SET	(0x00000714)
#define HW_PINCTRL_DOUT1_CLR	(0x00000718)
#define HW_PINCTRL_DOUT1_TOG	(0x0000071c)

#define BP_PINCTRL_DOUT1_DOUT	0
#define BM_PINCTRL_DOUT1_DOUT	0xFFFFFFFF
#define BF_PINCTRL_DOUT1_DOUT(v)	(v)

#define HW_PINCTRL_DOUT2	(0x00000720)
#define HW_PINCTRL_DOUT2_SET	(0x00000724)
#define HW_PINCTRL_DOUT2_CLR	(0x00000728)
#define HW_PINCTRL_DOUT2_TOG	(0x0000072c)

#define BP_PINCTRL_DOUT2_RSRVD1	28
#define BM_PINCTRL_DOUT2_RSRVD1	0xF0000000
#define BF_PINCTRL_DOUT2_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_DOUT2_RSRVD1)
#define BP_PINCTRL_DOUT2_DOUT	0
#define BM_PINCTRL_DOUT2_DOUT	0x0FFFFFFF
#define BF_PINCTRL_DOUT2_DOUT(v)  \
		(((v) << 0) & BM_PINCTRL_DOUT2_DOUT)

#define HW_PINCTRL_DOUT3	(0x00000730)
#define HW_PINCTRL_DOUT3_SET	(0x00000734)
#define HW_PINCTRL_DOUT3_CLR	(0x00000738)
#define HW_PINCTRL_DOUT3_TOG	(0x0000073c)

#define BM_PINCTRL_DOUT3_RSRVD1	0x80000000
#define BP_PINCTRL_DOUT3_DOUT	0
#define BM_PINCTRL_DOUT3_DOUT	0x7FFFFFFF
#define BF_PINCTRL_DOUT3_DOUT(v)  \
		(((v) << 0) & BM_PINCTRL_DOUT3_DOUT)

#define HW_PINCTRL_DOUT4	(0x00000740)
#define HW_PINCTRL_DOUT4_SET	(0x00000744)
#define HW_PINCTRL_DOUT4_CLR	(0x00000748)
#define HW_PINCTRL_DOUT4_TOG	(0x0000074c)

#define BP_PINCTRL_DOUT4_RSRVD1	21
#define BM_PINCTRL_DOUT4_RSRVD1	0xFFE00000
#define BF_PINCTRL_DOUT4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_DOUT4_RSRVD1)
#define BP_PINCTRL_DOUT4_DOUT	0
#define BM_PINCTRL_DOUT4_DOUT	0x001FFFFF
#define BF_PINCTRL_DOUT4_DOUT(v)  \
		(((v) << 0) & BM_PINCTRL_DOUT4_DOUT)

#define HW_PINCTRL_DIN0	(0x00000900)
#define HW_PINCTRL_DIN0_SET	(0x00000904)
#define HW_PINCTRL_DIN0_CLR	(0x00000908)
#define HW_PINCTRL_DIN0_TOG	(0x0000090c)

#define BP_PINCTRL_DIN0_RSRVD1	29
#define BM_PINCTRL_DIN0_RSRVD1	0xE0000000
#define BF_PINCTRL_DIN0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_DIN0_RSRVD1)
#define BP_PINCTRL_DIN0_DIN	0
#define BM_PINCTRL_DIN0_DIN	0x1FFFFFFF
#define BF_PINCTRL_DIN0_DIN(v)  \
		(((v) << 0) & BM_PINCTRL_DIN0_DIN)

#define HW_PINCTRL_DIN1	(0x00000910)
#define HW_PINCTRL_DIN1_SET	(0x00000914)
#define HW_PINCTRL_DIN1_CLR	(0x00000918)
#define HW_PINCTRL_DIN1_TOG	(0x0000091c)

#define BP_PINCTRL_DIN1_DIN	0
#define BM_PINCTRL_DIN1_DIN	0xFFFFFFFF
#define BF_PINCTRL_DIN1_DIN(v)	(v)

#define HW_PINCTRL_DIN2	(0x00000920)
#define HW_PINCTRL_DIN2_SET	(0x00000924)
#define HW_PINCTRL_DIN2_CLR	(0x00000928)
#define HW_PINCTRL_DIN2_TOG	(0x0000092c)

#define BP_PINCTRL_DIN2_RSRVD1	28
#define BM_PINCTRL_DIN2_RSRVD1	0xF0000000
#define BF_PINCTRL_DIN2_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_DIN2_RSRVD1)
#define BP_PINCTRL_DIN2_DIN	0
#define BM_PINCTRL_DIN2_DIN	0x0FFFFFFF
#define BF_PINCTRL_DIN2_DIN(v)  \
		(((v) << 0) & BM_PINCTRL_DIN2_DIN)

#define HW_PINCTRL_DIN3	(0x00000930)
#define HW_PINCTRL_DIN3_SET	(0x00000934)
#define HW_PINCTRL_DIN3_CLR	(0x00000938)
#define HW_PINCTRL_DIN3_TOG	(0x0000093c)

#define BM_PINCTRL_DIN3_RSRVD1	0x80000000
#define BP_PINCTRL_DIN3_DIN	0
#define BM_PINCTRL_DIN3_DIN	0x7FFFFFFF
#define BF_PINCTRL_DIN3_DIN(v)  \
		(((v) << 0) & BM_PINCTRL_DIN3_DIN)

#define HW_PINCTRL_DIN4	(0x00000940)
#define HW_PINCTRL_DIN4_SET	(0x00000944)
#define HW_PINCTRL_DIN4_CLR	(0x00000948)
#define HW_PINCTRL_DIN4_TOG	(0x0000094c)

#define BP_PINCTRL_DIN4_RSRVD1	21
#define BM_PINCTRL_DIN4_RSRVD1	0xFFE00000
#define BF_PINCTRL_DIN4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_DIN4_RSRVD1)
#define BP_PINCTRL_DIN4_DIN	0
#define BM_PINCTRL_DIN4_DIN	0x001FFFFF
#define BF_PINCTRL_DIN4_DIN(v)  \
		(((v) << 0) & BM_PINCTRL_DIN4_DIN)

#define HW_PINCTRL_DOE0	(0x00000b00)
#define HW_PINCTRL_DOE0_SET	(0x00000b04)
#define HW_PINCTRL_DOE0_CLR	(0x00000b08)
#define HW_PINCTRL_DOE0_TOG	(0x00000b0c)

#define BP_PINCTRL_DOE0_RSRVD1	29
#define BM_PINCTRL_DOE0_RSRVD1	0xE0000000
#define BF_PINCTRL_DOE0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_DOE0_RSRVD1)
#define BP_PINCTRL_DOE0_DOE	0
#define BM_PINCTRL_DOE0_DOE	0x1FFFFFFF
#define BF_PINCTRL_DOE0_DOE(v)  \
		(((v) << 0) & BM_PINCTRL_DOE0_DOE)

#define HW_PINCTRL_DOE1	(0x00000b10)
#define HW_PINCTRL_DOE1_SET	(0x00000b14)
#define HW_PINCTRL_DOE1_CLR	(0x00000b18)
#define HW_PINCTRL_DOE1_TOG	(0x00000b1c)

#define BP_PINCTRL_DOE1_DOE	0
#define BM_PINCTRL_DOE1_DOE	0xFFFFFFFF
#define BF_PINCTRL_DOE1_DOE(v)	(v)

#define HW_PINCTRL_DOE2	(0x00000b20)
#define HW_PINCTRL_DOE2_SET	(0x00000b24)
#define HW_PINCTRL_DOE2_CLR	(0x00000b28)
#define HW_PINCTRL_DOE2_TOG	(0x00000b2c)

#define BP_PINCTRL_DOE2_RSRVD1	28
#define BM_PINCTRL_DOE2_RSRVD1	0xF0000000
#define BF_PINCTRL_DOE2_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_DOE2_RSRVD1)
#define BP_PINCTRL_DOE2_DOE	0
#define BM_PINCTRL_DOE2_DOE	0x0FFFFFFF
#define BF_PINCTRL_DOE2_DOE(v)  \
		(((v) << 0) & BM_PINCTRL_DOE2_DOE)

#define HW_PINCTRL_DOE3	(0x00000b30)
#define HW_PINCTRL_DOE3_SET	(0x00000b34)
#define HW_PINCTRL_DOE3_CLR	(0x00000b38)
#define HW_PINCTRL_DOE3_TOG	(0x00000b3c)

#define BM_PINCTRL_DOE3_RSRVD1	0x80000000
#define BP_PINCTRL_DOE3_DOE	0
#define BM_PINCTRL_DOE3_DOE	0x7FFFFFFF
#define BF_PINCTRL_DOE3_DOE(v)  \
		(((v) << 0) & BM_PINCTRL_DOE3_DOE)

#define HW_PINCTRL_DOE4	(0x00000b40)
#define HW_PINCTRL_DOE4_SET	(0x00000b44)
#define HW_PINCTRL_DOE4_CLR	(0x00000b48)
#define HW_PINCTRL_DOE4_TOG	(0x00000b4c)

#define BP_PINCTRL_DOE4_RSRVD1	21
#define BM_PINCTRL_DOE4_RSRVD1	0xFFE00000
#define BF_PINCTRL_DOE4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_DOE4_RSRVD1)
#define BP_PINCTRL_DOE4_DOE	0
#define BM_PINCTRL_DOE4_DOE	0x001FFFFF
#define BF_PINCTRL_DOE4_DOE(v)  \
		(((v) << 0) & BM_PINCTRL_DOE4_DOE)

#define HW_PINCTRL_PIN2IRQ0	(0x00001000)
#define HW_PINCTRL_PIN2IRQ0_SET	(0x00001004)
#define HW_PINCTRL_PIN2IRQ0_CLR	(0x00001008)
#define HW_PINCTRL_PIN2IRQ0_TOG	(0x0000100c)

#define BP_PINCTRL_PIN2IRQ0_RSRVD1	29
#define BM_PINCTRL_PIN2IRQ0_RSRVD1	0xE0000000
#define BF_PINCTRL_PIN2IRQ0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_PIN2IRQ0_RSRVD1)
#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ	0
#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ	0x1FFFFFFF
#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v)  \
		(((v) << 0) & BM_PINCTRL_PIN2IRQ0_PIN2IRQ)

#define HW_PINCTRL_PIN2IRQ1	(0x00001010)
#define HW_PINCTRL_PIN2IRQ1_SET	(0x00001014)
#define HW_PINCTRL_PIN2IRQ1_CLR	(0x00001018)
#define HW_PINCTRL_PIN2IRQ1_TOG	(0x0000101c)

#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ	0
#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ	0xFFFFFFFF
#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v)	(v)

#define HW_PINCTRL_PIN2IRQ2	(0x00001020)
#define HW_PINCTRL_PIN2IRQ2_SET	(0x00001024)
#define HW_PINCTRL_PIN2IRQ2_CLR	(0x00001028)
#define HW_PINCTRL_PIN2IRQ2_TOG	(0x0000102c)

#define BP_PINCTRL_PIN2IRQ2_RSRVD1	28
#define BM_PINCTRL_PIN2IRQ2_RSRVD1	0xF0000000
#define BF_PINCTRL_PIN2IRQ2_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_PIN2IRQ2_RSRVD1)
#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ	0
#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ	0x0FFFFFFF
#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v)  \
		(((v) << 0) & BM_PINCTRL_PIN2IRQ2_PIN2IRQ)

#define HW_PINCTRL_PIN2IRQ3	(0x00001030)
#define HW_PINCTRL_PIN2IRQ3_SET	(0x00001034)
#define HW_PINCTRL_PIN2IRQ3_CLR	(0x00001038)
#define HW_PINCTRL_PIN2IRQ3_TOG	(0x0000103c)

#define BM_PINCTRL_PIN2IRQ3_RSRVD1	0x80000000
#define BP_PINCTRL_PIN2IRQ3_PIN2IRQ	0
#define BM_PINCTRL_PIN2IRQ3_PIN2IRQ	0x7FFFFFFF
#define BF_PINCTRL_PIN2IRQ3_PIN2IRQ(v)  \
		(((v) << 0) & BM_PINCTRL_PIN2IRQ3_PIN2IRQ)

#define HW_PINCTRL_PIN2IRQ4	(0x00001040)
#define HW_PINCTRL_PIN2IRQ4_SET	(0x00001044)
#define HW_PINCTRL_PIN2IRQ4_CLR	(0x00001048)
#define HW_PINCTRL_PIN2IRQ4_TOG	(0x0000104c)

#define BP_PINCTRL_PIN2IRQ4_RSRVD1	21
#define BM_PINCTRL_PIN2IRQ4_RSRVD1	0xFFE00000
#define BF_PINCTRL_PIN2IRQ4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_PIN2IRQ4_RSRVD1)
#define BP_PINCTRL_PIN2IRQ4_PIN2IRQ	0
#define BM_PINCTRL_PIN2IRQ4_PIN2IRQ	0x001FFFFF
#define BF_PINCTRL_PIN2IRQ4_PIN2IRQ(v)  \
		(((v) << 0) & BM_PINCTRL_PIN2IRQ4_PIN2IRQ)

#define HW_PINCTRL_IRQEN0	(0x00001100)
#define HW_PINCTRL_IRQEN0_SET	(0x00001104)
#define HW_PINCTRL_IRQEN0_CLR	(0x00001108)
#define HW_PINCTRL_IRQEN0_TOG	(0x0000110c)

#define BP_PINCTRL_IRQEN0_RSRVD1	29
#define BM_PINCTRL_IRQEN0_RSRVD1	0xE0000000
#define BF_PINCTRL_IRQEN0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_IRQEN0_RSRVD1)
#define BP_PINCTRL_IRQEN0_IRQEN	0
#define BM_PINCTRL_IRQEN0_IRQEN	0x1FFFFFFF
#define BF_PINCTRL_IRQEN0_IRQEN(v)  \
		(((v) << 0) & BM_PINCTRL_IRQEN0_IRQEN)

#define HW_PINCTRL_IRQEN1	(0x00001110)
#define HW_PINCTRL_IRQEN1_SET	(0x00001114)
#define HW_PINCTRL_IRQEN1_CLR	(0x00001118)
#define HW_PINCTRL_IRQEN1_TOG	(0x0000111c)

#define BP_PINCTRL_IRQEN1_IRQEN	0
#define BM_PINCTRL_IRQEN1_IRQEN	0xFFFFFFFF
#define BF_PINCTRL_IRQEN1_IRQEN(v)	(v)

#define HW_PINCTRL_IRQEN2	(0x00001120)
#define HW_PINCTRL_IRQEN2_SET	(0x00001124)
#define HW_PINCTRL_IRQEN2_CLR	(0x00001128)
#define HW_PINCTRL_IRQEN2_TOG	(0x0000112c)

#define BP_PINCTRL_IRQEN2_RSRVD1	28
#define BM_PINCTRL_IRQEN2_RSRVD1	0xF0000000
#define BF_PINCTRL_IRQEN2_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_IRQEN2_RSRVD1)
#define BP_PINCTRL_IRQEN2_IRQEN	0
#define BM_PINCTRL_IRQEN2_IRQEN	0x0FFFFFFF
#define BF_PINCTRL_IRQEN2_IRQEN(v)  \
		(((v) << 0) & BM_PINCTRL_IRQEN2_IRQEN)

#define HW_PINCTRL_IRQEN3	(0x00001130)
#define HW_PINCTRL_IRQEN3_SET	(0x00001134)
#define HW_PINCTRL_IRQEN3_CLR	(0x00001138)
#define HW_PINCTRL_IRQEN3_TOG	(0x0000113c)

#define BM_PINCTRL_IRQEN3_RSRVD1	0x80000000
#define BP_PINCTRL_IRQEN3_IRQEN	0
#define BM_PINCTRL_IRQEN3_IRQEN	0x7FFFFFFF
#define BF_PINCTRL_IRQEN3_IRQEN(v)  \
		(((v) << 0) & BM_PINCTRL_IRQEN3_IRQEN)

#define HW_PINCTRL_IRQEN4	(0x00001140)
#define HW_PINCTRL_IRQEN4_SET	(0x00001144)
#define HW_PINCTRL_IRQEN4_CLR	(0x00001148)
#define HW_PINCTRL_IRQEN4_TOG	(0x0000114c)

#define BP_PINCTRL_IRQEN4_RSRVD1	21
#define BM_PINCTRL_IRQEN4_RSRVD1	0xFFE00000
#define BF_PINCTRL_IRQEN4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_IRQEN4_RSRVD1)
#define BP_PINCTRL_IRQEN4_IRQEN	0
#define BM_PINCTRL_IRQEN4_IRQEN	0x001FFFFF
#define BF_PINCTRL_IRQEN4_IRQEN(v)  \
		(((v) << 0) & BM_PINCTRL_IRQEN4_IRQEN)

#define HW_PINCTRL_IRQLEVEL0	(0x00001200)
#define HW_PINCTRL_IRQLEVEL0_SET	(0x00001204)
#define HW_PINCTRL_IRQLEVEL0_CLR	(0x00001208)
#define HW_PINCTRL_IRQLEVEL0_TOG	(0x0000120c)

#define BP_PINCTRL_IRQLEVEL0_RSRVD1	29
#define BM_PINCTRL_IRQLEVEL0_RSRVD1	0xE0000000
#define BF_PINCTRL_IRQLEVEL0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_IRQLEVEL0_RSRVD1)
#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL	0
#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL	0x1FFFFFFF
#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v)  \
		(((v) << 0) & BM_PINCTRL_IRQLEVEL0_IRQLEVEL)

#define HW_PINCTRL_IRQLEVEL1	(0x00001210)
#define HW_PINCTRL_IRQLEVEL1_SET	(0x00001214)
#define HW_PINCTRL_IRQLEVEL1_CLR	(0x00001218)
#define HW_PINCTRL_IRQLEVEL1_TOG	(0x0000121c)

#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL	0
#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL	0xFFFFFFFF
#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v)	(v)

#define HW_PINCTRL_IRQLEVEL2	(0x00001220)
#define HW_PINCTRL_IRQLEVEL2_SET	(0x00001224)
#define HW_PINCTRL_IRQLEVEL2_CLR	(0x00001228)
#define HW_PINCTRL_IRQLEVEL2_TOG	(0x0000122c)

#define BP_PINCTRL_IRQLEVEL2_RSRVD1	28
#define BM_PINCTRL_IRQLEVEL2_RSRVD1	0xF0000000
#define BF_PINCTRL_IRQLEVEL2_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_IRQLEVEL2_RSRVD1)
#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL	0
#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL	0x0FFFFFFF
#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v)  \
		(((v) << 0) & BM_PINCTRL_IRQLEVEL2_IRQLEVEL)

#define HW_PINCTRL_IRQLEVEL3	(0x00001230)
#define HW_PINCTRL_IRQLEVEL3_SET	(0x00001234)
#define HW_PINCTRL_IRQLEVEL3_CLR	(0x00001238)
#define HW_PINCTRL_IRQLEVEL3_TOG	(0x0000123c)

#define BM_PINCTRL_IRQLEVEL3_RSRVD1	0x80000000
#define BP_PINCTRL_IRQLEVEL3_IRQLEVEL	0
#define BM_PINCTRL_IRQLEVEL3_IRQLEVEL	0x7FFFFFFF
#define BF_PINCTRL_IRQLEVEL3_IRQLEVEL(v)  \
		(((v) << 0) & BM_PINCTRL_IRQLEVEL3_IRQLEVEL)

#define HW_PINCTRL_IRQLEVEL4	(0x00001240)
#define HW_PINCTRL_IRQLEVEL4_SET	(0x00001244)
#define HW_PINCTRL_IRQLEVEL4_CLR	(0x00001248)
#define HW_PINCTRL_IRQLEVEL4_TOG	(0x0000124c)

#define BP_PINCTRL_IRQLEVEL4_RSRVD1	21
#define BM_PINCTRL_IRQLEVEL4_RSRVD1	0xFFE00000
#define BF_PINCTRL_IRQLEVEL4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_IRQLEVEL4_RSRVD1)
#define BP_PINCTRL_IRQLEVEL4_IRQLEVEL	0
#define BM_PINCTRL_IRQLEVEL4_IRQLEVEL	0x001FFFFF
#define BF_PINCTRL_IRQLEVEL4_IRQLEVEL(v)  \
		(((v) << 0) & BM_PINCTRL_IRQLEVEL4_IRQLEVEL)

#define HW_PINCTRL_IRQPOL0	(0x00001300)
#define HW_PINCTRL_IRQPOL0_SET	(0x00001304)
#define HW_PINCTRL_IRQPOL0_CLR	(0x00001308)
#define HW_PINCTRL_IRQPOL0_TOG	(0x0000130c)

#define BP_PINCTRL_IRQPOL0_RSRVD1	29
#define BM_PINCTRL_IRQPOL0_RSRVD1	0xE0000000
#define BF_PINCTRL_IRQPOL0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_IRQPOL0_RSRVD1)
#define BP_PINCTRL_IRQPOL0_IRQPOL	0
#define BM_PINCTRL_IRQPOL0_IRQPOL	0x1FFFFFFF
#define BF_PINCTRL_IRQPOL0_IRQPOL(v)  \
		(((v) << 0) & BM_PINCTRL_IRQPOL0_IRQPOL)

#define HW_PINCTRL_IRQPOL1	(0x00001310)
#define HW_PINCTRL_IRQPOL1_SET	(0x00001314)
#define HW_PINCTRL_IRQPOL1_CLR	(0x00001318)
#define HW_PINCTRL_IRQPOL1_TOG	(0x0000131c)

#define BP_PINCTRL_IRQPOL1_IRQPOL	0
#define BM_PINCTRL_IRQPOL1_IRQPOL	0xFFFFFFFF
#define BF_PINCTRL_IRQPOL1_IRQPOL(v)	(v)

#define HW_PINCTRL_IRQPOL2	(0x00001320)
#define HW_PINCTRL_IRQPOL2_SET	(0x00001324)
#define HW_PINCTRL_IRQPOL2_CLR	(0x00001328)
#define HW_PINCTRL_IRQPOL2_TOG	(0x0000132c)

#define BP_PINCTRL_IRQPOL2_RSRVD1	28
#define BM_PINCTRL_IRQPOL2_RSRVD1	0xF0000000
#define BF_PINCTRL_IRQPOL2_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_IRQPOL2_RSRVD1)
#define BP_PINCTRL_IRQPOL2_IRQPOL	0
#define BM_PINCTRL_IRQPOL2_IRQPOL	0x0FFFFFFF
#define BF_PINCTRL_IRQPOL2_IRQPOL(v)  \
		(((v) << 0) & BM_PINCTRL_IRQPOL2_IRQPOL)

#define HW_PINCTRL_IRQPOL3	(0x00001330)
#define HW_PINCTRL_IRQPOL3_SET	(0x00001334)
#define HW_PINCTRL_IRQPOL3_CLR	(0x00001338)
#define HW_PINCTRL_IRQPOL3_TOG	(0x0000133c)

#define BM_PINCTRL_IRQPOL3_RSRVD1	0x80000000
#define BP_PINCTRL_IRQPOL3_IRQPOL	0
#define BM_PINCTRL_IRQPOL3_IRQPOL	0x7FFFFFFF
#define BF_PINCTRL_IRQPOL3_IRQPOL(v)  \
		(((v) << 0) & BM_PINCTRL_IRQPOL3_IRQPOL)

#define HW_PINCTRL_IRQPOL4	(0x00001340)
#define HW_PINCTRL_IRQPOL4_SET	(0x00001344)
#define HW_PINCTRL_IRQPOL4_CLR	(0x00001348)
#define HW_PINCTRL_IRQPOL4_TOG	(0x0000134c)

#define BP_PINCTRL_IRQPOL4_RSRVD1	21
#define BM_PINCTRL_IRQPOL4_RSRVD1	0xFFE00000
#define BF_PINCTRL_IRQPOL4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_IRQPOL4_RSRVD1)
#define BP_PINCTRL_IRQPOL4_IRQPOL	0
#define BM_PINCTRL_IRQPOL4_IRQPOL	0x001FFFFF
#define BF_PINCTRL_IRQPOL4_IRQPOL(v)  \
		(((v) << 0) & BM_PINCTRL_IRQPOL4_IRQPOL)

#define HW_PINCTRL_IRQSTAT0	(0x00001400)
#define HW_PINCTRL_IRQSTAT0_SET	(0x00001404)
#define HW_PINCTRL_IRQSTAT0_CLR	(0x00001408)
#define HW_PINCTRL_IRQSTAT0_TOG	(0x0000140c)

#define BP_PINCTRL_IRQSTAT0_RSRVD1	29
#define BM_PINCTRL_IRQSTAT0_RSRVD1	0xE0000000
#define BF_PINCTRL_IRQSTAT0_RSRVD1(v) \
		(((v) << 29) & BM_PINCTRL_IRQSTAT0_RSRVD1)
#define BP_PINCTRL_IRQSTAT0_IRQSTAT	0
#define BM_PINCTRL_IRQSTAT0_IRQSTAT	0x1FFFFFFF
#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v)  \
		(((v) << 0) & BM_PINCTRL_IRQSTAT0_IRQSTAT)

#define HW_PINCTRL_IRQSTAT1	(0x00001410)
#define HW_PINCTRL_IRQSTAT1_SET	(0x00001414)
#define HW_PINCTRL_IRQSTAT1_CLR	(0x00001418)
#define HW_PINCTRL_IRQSTAT1_TOG	(0x0000141c)

#define BP_PINCTRL_IRQSTAT1_IRQSTAT	0
#define BM_PINCTRL_IRQSTAT1_IRQSTAT	0xFFFFFFFF
#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v)	(v)

#define HW_PINCTRL_IRQSTAT2	(0x00001420)
#define HW_PINCTRL_IRQSTAT2_SET	(0x00001424)
#define HW_PINCTRL_IRQSTAT2_CLR	(0x00001428)
#define HW_PINCTRL_IRQSTAT2_TOG	(0x0000142c)

#define BP_PINCTRL_IRQSTAT2_RSRVD1	28
#define BM_PINCTRL_IRQSTAT2_RSRVD1	0xF0000000
#define BF_PINCTRL_IRQSTAT2_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_IRQSTAT2_RSRVD1)
#define BP_PINCTRL_IRQSTAT2_IRQSTAT	0
#define BM_PINCTRL_IRQSTAT2_IRQSTAT	0x0FFFFFFF
#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v)  \
		(((v) << 0) & BM_PINCTRL_IRQSTAT2_IRQSTAT)

#define HW_PINCTRL_IRQSTAT3	(0x00001430)
#define HW_PINCTRL_IRQSTAT3_SET	(0x00001434)
#define HW_PINCTRL_IRQSTAT3_CLR	(0x00001438)
#define HW_PINCTRL_IRQSTAT3_TOG	(0x0000143c)

#define BM_PINCTRL_IRQSTAT3_RSRVD1	0x80000000
#define BP_PINCTRL_IRQSTAT3_IRQSTAT	0
#define BM_PINCTRL_IRQSTAT3_IRQSTAT	0x7FFFFFFF
#define BF_PINCTRL_IRQSTAT3_IRQSTAT(v)  \
		(((v) << 0) & BM_PINCTRL_IRQSTAT3_IRQSTAT)

#define HW_PINCTRL_IRQSTAT4	(0x00001440)
#define HW_PINCTRL_IRQSTAT4_SET	(0x00001444)
#define HW_PINCTRL_IRQSTAT4_CLR	(0x00001448)
#define HW_PINCTRL_IRQSTAT4_TOG	(0x0000144c)

#define BP_PINCTRL_IRQSTAT4_RSRVD1	21
#define BM_PINCTRL_IRQSTAT4_RSRVD1	0xFFE00000
#define BF_PINCTRL_IRQSTAT4_RSRVD1(v) \
		(((v) << 21) & BM_PINCTRL_IRQSTAT4_RSRVD1)
#define BP_PINCTRL_IRQSTAT4_IRQSTAT	0
#define BM_PINCTRL_IRQSTAT4_IRQSTAT	0x001FFFFF
#define BF_PINCTRL_IRQSTAT4_IRQSTAT(v)  \
		(((v) << 0) & BM_PINCTRL_IRQSTAT4_IRQSTAT)

#define HW_PINCTRL_EMI_ODT_CTRL	(0x00001a40)
#define HW_PINCTRL_EMI_ODT_CTRL_SET	(0x00001a44)
#define HW_PINCTRL_EMI_ODT_CTRL_CLR	(0x00001a48)
#define HW_PINCTRL_EMI_ODT_CTRL_TOG	(0x00001a4c)

#define BP_PINCTRL_EMI_ODT_CTRL_RSRVD1	28
#define BM_PINCTRL_EMI_ODT_CTRL_RSRVD1	0xF0000000
#define BF_PINCTRL_EMI_ODT_CTRL_RSRVD1(v) \
		(((v) << 28) & BM_PINCTRL_EMI_ODT_CTRL_RSRVD1)
#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB	26
#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB	0x0C000000
#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB(v)  \
		(((v) << 26) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB)
#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD	24
#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD	0x03000000
#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD(v)  \
		(((v) << 24) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD)
#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB	22
#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB	0x00C00000
#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB(v)  \
		(((v) << 22) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB)
#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD	20
#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD	0x00300000
#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD(v)  \
		(((v) << 20) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD)
#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB	18
#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB	0x000C0000
#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB(v)  \
		(((v) << 18) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB)
#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD	16
#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD	0x00030000
#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD(v)  \
		(((v) << 16) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD)
#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB	14
#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB	0x0000C000
#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB(v)  \
		(((v) << 14) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB)
#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD	12
#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD	0x00003000
#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD(v)  \
		(((v) << 12) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD)
#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB	10
#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB	0x00000C00
#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB(v)  \
		(((v) << 10) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB)
#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD	8
#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD	0x00000300
#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD(v)  \
		(((v) << 8) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD)
#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB	6
#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB	0x000000C0
#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB(v)  \
		(((v) << 6) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB)
#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD	4
#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD	0x00000030
#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD(v)  \
		(((v) << 4) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD)
#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB	2
#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB	0x0000000C
#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB(v)  \
		(((v) << 2) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB)
#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD	0
#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD	0x00000003
#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD(v)  \
		(((v) << 0) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD)

#define HW_PINCTRL_EMI_DS_CTRL	(0x00001b80)
#define HW_PINCTRL_EMI_DS_CTRL_SET	(0x00001b84)
#define HW_PINCTRL_EMI_DS_CTRL_CLR	(0x00001b88)
#define HW_PINCTRL_EMI_DS_CTRL_TOG	(0x00001b8c)

#define BP_PINCTRL_EMI_DS_CTRL_RSRVD1	18
#define BM_PINCTRL_EMI_DS_CTRL_RSRVD1	0xFFFC0000
#define BF_PINCTRL_EMI_DS_CTRL_RSRVD1(v) \
		(((v) << 18) & BM_PINCTRL_EMI_DS_CTRL_RSRVD1)
#define BP_PINCTRL_EMI_DS_CTRL_DDR_MODE	16
#define BM_PINCTRL_EMI_DS_CTRL_DDR_MODE	0x00030000
#define BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(v)  \
		(((v) << 16) & BM_PINCTRL_EMI_DS_CTRL_DDR_MODE)
#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__mDDR   00
#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__GPIO   01
#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__LVDDR2 10
#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__DDR2   11
#define BP_PINCTRL_EMI_DS_CTRL_RSRVD0	14
#define BM_PINCTRL_EMI_DS_CTRL_RSRVD0	0x0000C000
#define BF_PINCTRL_EMI_DS_CTRL_RSRVD0(v)  \
		(((v) << 14) & BM_PINCTRL_EMI_DS_CTRL_RSRVD0)
#define BP_PINCTRL_EMI_DS_CTRL_ADDRESS_MA	12
#define BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA	0x00003000
#define BF_PINCTRL_EMI_DS_CTRL_ADDRESS_MA(v)  \
		(((v) << 12) & BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA)
#define BP_PINCTRL_EMI_DS_CTRL_CONTROL_MA	10
#define BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA	0x00000C00
#define BF_PINCTRL_EMI_DS_CTRL_CONTROL_MA(v)  \
		(((v) << 10) & BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA)
#define BP_PINCTRL_EMI_DS_CTRL_DUALPAD_MA	8
#define BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA	0x00000300
#define BF_PINCTRL_EMI_DS_CTRL_DUALPAD_MA(v)  \
		(((v) << 8) & BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA)
#define BP_PINCTRL_EMI_DS_CTRL_SLICE3_MA	6
#define BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA	0x000000C0
#define BF_PINCTRL_EMI_DS_CTRL_SLICE3_MA(v)  \
		(((v) << 6) & BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA)
#define BP_PINCTRL_EMI_DS_CTRL_SLICE2_MA	4
#define BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA	0x00000030
#define BF_PINCTRL_EMI_DS_CTRL_SLICE2_MA(v)  \
		(((v) << 4) & BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA)
#define BP_PINCTRL_EMI_DS_CTRL_SLICE1_MA	2
#define BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA	0x0000000C
#define BF_PINCTRL_EMI_DS_CTRL_SLICE1_MA(v)  \
		(((v) << 2) & BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA)
#define BP_PINCTRL_EMI_DS_CTRL_SLICE0_MA	0
#define BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA	0x00000003
#define BF_PINCTRL_EMI_DS_CTRL_SLICE0_MA(v)  \
		(((v) << 0) & BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA)
#endif /* __ARCH_ARM___PINCTRL_H */
